print

Areeba : an area efficient binary huff-curve architecture

author
Sajid, Asher
Rashid, Muhammad
Jamal, Sajjad Shaukat
Imran, Malik
Alotaibi, Saud S.
Sinky, Mohammed H.
statement of authorship
Asher Sajid, Muhammad Rashid, Sajjad Shaukat Jamal, Malik Imran, Saud S. Alotaibi and Mohammed H. Sinky
source
Electronics (Switzerland)
publisher
MDPI
journal volume number month
Vol. 10, 12
year of publication
2021
pages
art. 1490
url
https://doi.org/10.3390/electronics10121490
subject term
krüptograafia
integraallülitused
riistvara
küberturve
keyword
area optimization
binary Huff curves
crypto processor
elliptic curve cryptography
Field Programmable Gate Array (FPGA)
ISSN
2079-9292
notes
Bibliogr.: 30 ref
Open Access
Open Access
scientific publication
teaduspublikatsioon
classifier
1.1
Scopus
Journal metrics at Scopus
Article at Scopus
WOS
Journal metrics at WOS
Article at WOS
category (general)
Engineering
Computer science
category (sub)
Engineering. Control and systems engineering
Engineering. Electrical and electronic engineering
Computer science. Computer networks and communications
Computer science. Signal processing
Computer science. Hardware and architecture
kvartiil
Q2
TTÜ department
arvutisüsteemide instituut
language
inglise
Uurimisrühm
Centre for hardware security
Sajid, A., Rashid, M., Jamal, S.S., Imran, M., Alotaibi, S.S., Sinky, M.H. Areeba : an area efficient binary huff-curve architecture // Electronics (Switzerland) (2021) Vol. 10, 12, art. 1490. https://doi.org/10.3390/electronics10121490