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Automatic SoC level test path synthesis based on partial functional models

author
statement of authorship
Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
source
2011 Asian Test Symposium (ATS) : New Delhi, India
location of publication
[S.l.]
year of publication
pages
p. 532-538
conference name, date
2011 Asian Test Symposium (ATS)
conference location
New Delhi, India
url
ISSN
1081-7735
language
inglise
subject term
keyword
processor-centric board test
test path synthesis
JTAG
decision diagrams
PCBA component modeling
Tšertov, A., Ubar, R., Jutman, A., Devadze, S. Automatic SoC level test path synthesis based on partial functional models // 2011 Asian Test Symposium (ATS) : New Delhi, India. [S.l.], 2011. p. 532-538. https://ieeexplore.ieee.org/document/6114730