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A constraint-driven gate-level test generator (title)
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book article
A constraint-driven gate-level test generator
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Jervan, Gert
;
Krupnova, Helena
BEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings
1996
/
p. 237-240: ill
book article
Number of records 1, displaying
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keyword
13
1.
gate-level analysis
2.
gate-level circuit abstraction
3.
gate-level netlist
4.
register transfer and gate level simulation
5.
test driven development
6.
test driven modelling
7.
behaviour level test generation
8.
Hierarchical Multi-level Test Generation
9.
high-level synthesis for test
10.
high-level test data generation
11.
system level test
12.
efficiency-driven and innovation-driven economies
13.
logic level and high level BDDs
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