Searching - TalTech Research Portal

Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles

Research Groups

Help and information

Searching

gate-level analysis (keyword)

—

—

—

—

Add criteria Advanced search filter

Clear

types of item

book ..

journal article ..

newspaper article ..

book article ..

dissertation ..

Open Access ..

Scientific publication ..

year

year of publication

Loading..

Loading..

TTÜ department

Loading..

Loading..

Loading..

name of the person

Loading..

Loading..

Clear

Number of records 3
Look more.. (1/138)
Export

export all inquiry results (3)
Save TXT fail

Save PDF fail

print
Open for editing with marked entries my bookmarks

display

sort
1

journal article EST / journal article ENG

Fast identification of true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, Jaan; Jürimägi, LembitMicroelectronics reliability2018 / p. 252-261 : ill https://doi.org/10.1016/j.microrel.2017.11.027 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG
2

book article

Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176

book article
3

book article

A scalable technique to identify true critical paths in sequential circuitsUbar, Raimund-Johannes; Kostin, Sergei; Jenihhin, Maksim; Raik, JaanProceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany2017 / p. 152-157 : ill https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553

book article

Number of records 3, displaying 1 - 3

1. gate-level analysis
2. gate-level circuit abstraction
3. gate-level netlist
4. register transfer and gate level simulation
5. hierarchical two-level analysis
6. system-level analysis
7. logic level and high level BDDs
8. Field Programmable Gate Array (FPGA)
9. field programmable gate arrays
10. field-programmable gate array
11. Field-Programmable Gate Array (FPGA)
12. field-programmable gate arrays
13. FPGA (field-programmable gate array)
14. GaTe
15. gate and register transfer levels
16. gate delay
17. gate driver
18. Gate Injection Transistor (GIT)
19. Golden gate assembly
20. insulated gate bipolar transistors
21. insulated gate-commutated thyristors
22. NBTI-critical gate
23. Opal Kelly ﬁeld programmable gate array (FPGA)
24. absolute sea level
25. airport level of service
26. arousal level
27. assurance level
28. behaviour level test generation
29. bi-level optimization
30. CO2 level in classrooms
31. CO2 level in classrooms and kindergartens
32. confidence level
33. country-level logistics
34. customer compatibility level
35. deep level
36. deep level traps
37. determination of the CO2 level
38. determining the level of creatine
39. digitalisation level
40. distribution-level phasor measurement units (D-PMUs)
41. exposure level
42. extreme penetration level of non synchronous generation
43. extreme water level
44. graduate level
45. high level DD (HLDD)
46. high level synthesis
47. high-level control fault model
48. high-level control faults
49. high-level decision diagram
50. high-level decision diagrams
51. high-level decision diagrams (HLDD) synthesis
52. high-level expert group on AI
53. high-level fault coverage
54. high-level fault model
55. high-level fault simulation
56. high-level functional fault model
57. High-Level Synthesis (HLS)
58. high-level synthesis for test
59. high-level test data generation
60. improvement of safety level at enterprises
61. improvement of safety level at SMEs
62. level control
63. level set
64. level(s) methodology
65. level-crossing ADC
66. level-crossing analog-to-digital converters
67. level-crossing analogue-to-digital converters (ADC)
68. logic level
69. lower trophic level models
70. low-level control system transportation
71. low-level fault redundancy
72. low-level radiation
73. Low-level RF EMF
74. macro-level industry influences
75. mean sea level
76. module level power electronics (MLPE)
77. module-level power electronics (MLPE)
78. multi-level governance
79. multi-level inverter
80. multi-level modeling
81. multi-level perspective
82. multi-level perspective of sustainability transitions
83. multi-level selection and processing environment
84. operational level (OL)
85. Price level
86. Process/Product Sigma Performance Level (PSPL)
87. PV module level power electronics
88. Register Transfer Level - RTL
89. register transfer level modeling decision diagams
90. register-transfer level
91. relative sea level
92. relative sea-level change
93. RH level
94. school-level policies
95. sea level
96. sea level rise
97. sea level series
98. sea level trend
99. sea level: variations and mean
100. sea-level
101. sea-level changes
102. sea-level equation
103. Sea-level indicator
104. sea-level prediction
105. sea-level rise
106. sea-level trend
107. seven-level multilevel
108. skin conductance level
109. software level TMR
110. steel-level bureaucracy
111. strategic level decision makers
112. system level hazards
113. system level test
114. system planning level
115. system-level evaluation
116. task-level uninterrupted presence
117. three-level
118. three-level inverter
119. three-level neutral-point-clamped inverter
120. three-level NPC inverter
121. three-level T-type
122. three-level T-type inverter
123. three-level T-type quasi-impedance-source inverter (3L-T-type qZSI)
124. three-level voltage inverter
125. Tool Confidence Level
126. top-level domain
127. transaction-level modeling
128. treatment level
129. two-level inverter
130. undergraduate level
131. water level
132. water level fluctuation
133. water level measurements
134. water level reconstruction
135. water-level changes
136. voltage level
137. voltage level optimisation
138. 3-level T-type inverter

match

sort

Otsing
Valikud 0

year of publication

author

TTÜ department

subject term

series

name of the person

keyword

TalTech Library

Akadeemia tee 1

13519

TalTech homepage TalTech Library homepage Digital Collection of TalTech Library Digiteek Repository

6203551

data@taltech.ee

TalTech Raamatukogu