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Formalization of finite state machines with data path for the verification of high-level synthesis (title)
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book article
Formalization of finite state machines with data path for the verification of high-level synthesis
Borrione, Dominique
;
Dušina, Julia
;
Pierre, Laurence
XI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings
1998
/
p. 99-102: ill
https://ieeexplore.ieee.org/document/715419
book article
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keyword
11
1.
finite-state machines
2.
verification, assertion-based verification, automatic assertion mining, data mining, association rule mining
3.
high level synthesis
4.
high-level decision diagrams (HLDD) synthesis
5.
high-level synthesis
6.
High-Level Synthesis (HLS)
7.
high-level synthesis for test
8.
high-level test data generation
9.
logic level and high level BDDs
10.
test path synthesis
11.
control and data path tests
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