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Pagliarini, Samuel Nascimento (supervisor)
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1
dissertation
Hardware realization of lattice-based post-quantum cryptography = Võrel põhinev post-kvant-krüptograafia riistvaraline realisatsioon
Imran, Malik
2023
https://www.ester.ee/record=b5571216*est
https://doi.org/10.23658/taltech.33/2023
https://digikogu.taltech.ee/et/Item/75aeb070-cb8b-4511-beaf-cbea3fca147d
https://www.ester.ee/record=b5571216*est
dissertation
Seotud publikatsioonid
6
An experimental study of building blocks of lattice-based NIST post-quantum cryptographic algorithms
An open-source library of large integer polynomial multipliers
Design space exploration of SABER in 65nm ASIC
High-speed SABER key encapsulation mechanism in 65nm CMOS
A versatile and flexible multiplier generator for Large integer polynomials
High-speed design of postquantum cryptography with optimized hashing and multiplication
2
dissertation
Leveraging FPGA Reconfigurability as an Obfuscation Asset = FPGA ümberkonfigureeritavuse rakendamine hägustamise vahendina
Abideen, Zain Ul
2024
https://digikogu.taltech.ee/et/Item/660d923b-44d2-4993-898f-324ab2088199
https://www.ester.ee/record=b5649944*est
https://doi.org/10.23658/taltech.1/2024
dissertation
Seotud publikatsioonid
4
From FPGAs to obfuscated eASICs : design and security trade-offs
A security-aware and LUT-based CAD flow for the physical synthesis of hASICs
Impact of orientation on the bias of SRAM-based PUFs
An overview of FPGA-inspired obfuscation techniques
3
dissertation
On the use of defensive schemes for hardware security = Kaitseskeemid riistvara turvalisuse tagamiseks
Eslami, Mohammad
2024
https://www.ester.ee/record=b5701420*est
https://doi.org/10.23658/taltech.53/2024
https://digikogu.taltech.ee/et/Item/068530be-4810-4489-9604-fb838d298b45
dissertation
Seotud publikatsioonid
4
Reusing verification assertions as security checkers for Hardware Trojan detection
Benchmarking advanced security closure of physical layouts
SALSy : security-aware layout synthesis
SCARF : securing chips with a robust framework against fabrication-time hardware Trojans : preprint
4
dissertation
Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline süntees
Perez, Tiago Diadami
2023
https://doi.org/10.23658/taltech.4/2023
https://digikogu.taltech.ee/et/Item/440f41fd-0950-4b5c-8e47-4f75a754cdae
https://www.ester.ee/record=b5536743*est
dissertation
Seotud publikatsioonid
6
Side-channel Trojan insertion - a practical foundry-side attack via ECO
G-GPU : a fully-automated generator of GPU-like ASIC accelerators
A survey on split manufacturing : attacks, defenses, and challenges
A pragmatic methodology for blind hardware trojan insertion in finalized layouts
Hardware trojan insertion in finalized layouts : from methodology to a silicon demonstration
A side-channel hardware trojan in 65nm CMOS with 2μW precision and multi-bit leakage capability
Number of records 4, displaying
1 - 4
author
18
1.
Pagliarini, Samuel Nascimento
2.
Nascimento, Douglas
3.
Silva, Roberto Nascimento
4.
Bankole, Olabode Samuel
5.
Deniaud, Samuel
6.
Dobrin, Samuel
7.
Foli, Samuel
8.
Glass, Samuel V.
9.
Klassen, Samuel
10.
Olsson, Samuel L. I.
11.
Samuel, Evelin
12.
Samuel, G.
13.
Samuel, Georgi
14.
Samuel, Külli
15.
Samuel, Titilola A.
16.
Samuel, Titilola Aderonke
17.
Wedaj, Samuel
18.
Viboud, Samuel
CV
3
1.
Pagliarini, Samuel Nascimento 1985
2.
Nascimento Pagliarini, Samuel
3.
Foli, Samuel 1996
name of the person
2
1.
Pagliarini, Samuel Nascimento
2.
Cohen, Samuel Theodore, 1921–2010
keyword
2
1.
Pierre Samuel Dupont de Nemours
2.
Samuel Huntington
subject term
1
1.
Samuel Besprosvanie, silmkoetööstus
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