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High-level path activation technique to speed up sequential circuit test generation (title)
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book article
High-level path activation technique to speed up sequential circuit test generation
Raik, Jaan
;
Ubar, Raimund-Johannes
European Test Workshop 1999 : proceedings, May 25-28, 1999, Constance, Germany
1999
/
p. 84-89 : ill
https://ieeexplore.ieee.org/document/804289
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keyword
9
1.
high-level test data generation
2.
high-speed serial link test
3.
behaviour level test generation
4.
Hierarchical Multi-level Test Generation
5.
high-level synthesis for test
6.
logic level and high level BDDs
7.
feasible path generation
8.
high energy milled activation
9.
test path synthesis
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