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Hierarchical defect-oriented fault simulation for digital circuits (title)
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book article
Hierarchical defect-oriented fault simulation for digital circuits
Blyzniuk, M.
;
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Lobur, M.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings
2000
/
p. 69-74 : ill
book article
2
book article
Hierarchical defect-oriented fault simulation for digital circuits
Blyzniuk, M.
;
Cibakova, Tatiana
;
Gramatova, Elena
;
Kuzmicz, W.
;
Lobur, M.
;
Pleskacz, Witold A.
;
Raik, Jaan
;
Ubar, Raimund-Johannes
IEEE European Test Workshop
2000
/
p. 151-156
https://ieeexplore.ieee.org/document/873781
book article
Number of records 2, displaying
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keyword
8
1.
digital circuits
2.
digital circuits and systems
3.
Fault Injection Simulation
4.
fault simulation
5.
fault simulation with critical path tracing
6.
high-level fault simulation
7.
parallel fault-simulation
8.
digital real time simulation
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