Hierarchical defect-oriented fault simulation for digital circuits
author
statement of authorship
M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar
source
IEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings
location of publication
Los Alamitos, CA
publisher
year of publication
pages
p. 69-74 : ill
ISBN
0-7695-0701-8
notes
Bibliogr.: 13 ref
Blyzniuk, M., Cibakova, T., Gramatova, E., Kuzmicz, W., Lobur, M., Pleskacz, W., Raik, J., Ubar, R. Hierarchical defect-oriented fault simulation for digital circuits // IEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings. Los Alamitos, CA : IEEE Computer Society, 2000. p. 69-74 : ill.