Layout to logic defect analysis for hierarchical test generation
statement of authorship
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
source
Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland
location of publication
[S.l.]
publisher
year of publication
pages
p. 35-40 : ill
conference name, date
10th IEEE Workshop on Design and Diagnostic Circuits and Systems, April 11-13, 2007
conference location
Krakow, Poland
subject term
notes
Bibliogr.: 17 ref
TTÜ department
language
inglise
Jenihhin, M., Raik, J., Ubar, R.-J., Pleskacz, W., Rakowski, M. Layout to logic defect analysis for hierarchical test generation // Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland. [S.l.] : IEEE, 2007. p. 35-40 : ill.