Layout to logic defect analysis for hierarchical test generation
vastutusandmed
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
allikas
Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland
ilmumiskoht
[S.l.]
kirjastus/väljaandja
ilmumisaasta
leheküljed
p. 35-40 : ill
konverentsi nimetus, aeg
10th IEEE Workshop on Design and Diagnostic Circuits and Systems, April 11-13, 2007
konverentsi toimumispaik
Krakow, Poland
märkused
Bibliogr.: 17 ref
TTÜ struktuuriüksus
keel
inglise
Jenihhin, M., Raik, J., Ubar, R.-J., Pleskacz, W., Rakowski, M. Layout to logic defect analysis for hierarchical test generation // Proceedings of the 2007 IEEE Workshop on Design and Diagnostic Circuits and Systems : April 11-13, 2007, Krakow, Poland. [S.l.] : IEEE, 2007. p. 35-40 : ill.