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High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

author
Oyeniran, Adeboye Stephen
Ubar, Raimund-Johannes
Jenihhin, Maksim
Raik, Jaan
statement of authorship
Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
source
2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings
location of publication
Danvers
publisher
IEEE
year of publication
2019
pages
6 p. : ill
conference location
Baden-Baden, Germany
url
https://doi.org/10.1109/ETS.2019.8791526
keyword
RISC processors
high-level fault model
high-level test data generation
deterministic and pseudo-exhaustive tests
control and data path tests
ISBN
978-1-7281-1173-5
notes
Bibliogr.: 31 ref
TTÜ department
arvutisüsteemide instituut
language
inglise
Oyeniran, A.S., Ubar, R., Jenihhin, M., Gürsoy, C., Raik, J. High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors // 2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings. Danvers : IEEE, 2019. 6 p. : ill. https://doi.org/10.1109/ETS.2019.8791526