prindi

Logic IP for low-cost IC design in advanced CMOS nodes

autor
Isgenc, Mehmet Meric
Martins, Mayler G.A.
Zackriya, V. Mohammed
Pagliarini, Samuel Nascimento
Pileggi, Larry
vastutusandmed
Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Larry Pileggi
allikas
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
kirjastus/väljaandja
IEEE
ajakirja aastakäik number kuu
vol. 28, no. 2
ilmumisaasta
2020
leheküljed
p. 585-595
leitav
https://doi.org//10.1109/TVLSI.2019.2942825
märksõna
arvuti arhitektuur
mikroprotsessorid
integraallülitused
disain
võtmesõna
Pins
Routing
Layout
Computer architecture
Microprocessors
Libraries
CMOS scaling
digital integrated circuit (IC) design
layout patterns
logic cell library
routing closure
ISSN
1063-8210
557-9999
märkused
Bibliogr.: 29 ref
TTÜ struktuuriüksus
arvutisüsteemide instituut
keel
inglise
Isgenc, M.M., Martins, M.G.A., Zackriya, M., Pagliarini, S.N., Pileggi, L. Logic IP for low-cost IC design in advanced CMOS nodes // IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2020) vol. 28, no. 2, p. 585-595. https://doi.org//10.1109/TVLSI.2019.2942825