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326

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Hierarchical test generation for complex digital systems with control and data processing partsUbar, Raimund-Johannes; Raik, Jaan"Test, Assembly and Packaging" : SEMICON Technical Symposium : Singapur, May 3-6, 19991999 / p. 43-52

book article

327

dissertation

Hierarchical test generation for digital circuits represented by Decision Diagrams : thesis on informatics and system engineeringRaik, Jaan2001 https://www.ester.ee/record=b1578107*est

dissertation

328

book article

Hierarchical test generation for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesMixed design of integrated circuits and systems1998 / p. 131-136: ill

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329

book article

Hierarchical test generation for digital systems based on combining bottom-up and top-down approachesRaik, Jaan; Ubar, Raimund-JohannesWorld Multiconference on Systemics, Cybernetics and Informatics, July 12-16, 1998, Orlando, Florida : proceedings. Vol. 11998 / p. 374-381: ill

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330

book article

Hierarchical test generation for finite state machinesBrik, Marina; Ubar, Raimund-JohannesBEC : Baltic Electronics Conference : proceedings of the 4th Biennial Conference, October 9-14, 1994, Tallinn (Estonia). 11994 / p. 319-324: ill

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331

book article

Hierarchical test generation with multi-level decision diagram modelsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 7th IEEE North Atlantic Test Workshop, West Greenwich RI, USA, May 28-29, 19981998 / p. 26-33

book article

332

book article

Hierarchical test generation. SEMI show slidesUbar, Raimund-Johannes; Raik, Jaan"Test, Assembly and Packaging" : SEMICON Technical Symposium : Singapur, May 3-6, 19991999 / p. 53-64

book article

333

book article

Hierarchical test synthesis for digital systems using alternative graph modelUbar, Raimund-JohannesQuantitative aspects of designing and validating dependable computing systems1995

book article

334

book article

Hierarchical timing-critical paths analysis in sequential circuitsJürimägi, Lembit; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan; Devadze, Sergei; Kostin, Sergei2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain2018 / 6 p. : ill https://doi.org/10.1109/PATMOS.2018.8464176

book article

335

book article

High level fault modeling in digital systemsUbar, Raimund-Johannes; Aarna, Margit; Brik, Marina; Raik, JaanSynergies between Information and Automation : 49. Internationales Wissenschaftliches Kolloquium, 27.-30.9.2004, Technische Universität Ilmenau, Germany. Volume 22004 / p. 486-491

book article

336

journal article

High quality test generation for digital systemsUbar, Raimund-Johannes; Aarna, Margit; Kruus, Helena; Raik, JaanRomanian journal of information science and technology2005 / 1, p. 73-84 : ill

journal article

337

book article

High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, Jaan2019 IEEE European Test Symposium (ETS) : ETS 2019, May 27-31, 2019, Baden-Baden, Germany : Proceedings2019 / 6 p. : ill https://doi.org/10.1109/ETS.2019.8791526

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338

book article

High-level combined deterministic and pseudo-exhuastive test generation for RISC processorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Gürsoy, Cemil Cem; Raik, Jaan2019 IEEE European Test Symposium (ETS) : proceedings2019 / 6 p. : ill https://doi.org/10.1109/ETS.2019.8791526

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339

book article

High-level decision diagram based fault models for targeting FSMsRaik, Jaan; Ubar, Raimund-Johannes; Viilukas, Taavi9th EUROMICRO Conference on Digital Systems Design : Architectures, Methods and Tools (DSD 2006) : 30 August 2006-1 September 2006, Cavtat near Dubrovnik, Croatia : proceedings2006 / p. 353-358 : ill http://dx.doi.org/10.1109/DSD.2006.60

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340

book article

High-Level Decision Diagram manipulations for code coverage analysisMinakova, Karina; Reinsalu, Uljana; Tšepurov, Anton; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes; Ellervee, PeeterBEC 2008 : 2008 International Biennial Baltic Electronics Conference : proceedings of the 11th Biennial Baltic Electronics Conference : Tallinn University of Technology : October 6-8, 2008, Tallinn, Estonia2008 / p. 207-210 : ill

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341

book article

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

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342

book article

High-level decision diagrams for improving simulation performance of digital systemsUbar, Raimund-Johannes; Raik, Jaan; Morawiec, AdamSCI 2000 : World Multiconference on Systemics, Cybernetics and Informatics : July 23-26, 2000, Orlando, Florida, USA : proceedings. Volume IX, Industrial Systems2000 / p. 62-67 : ill

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343

book article

High-level design error diagnosis using backtrace on decision diagramsRaik, Jaan; Repinski, Urmas; Ubar, Raimund-Johannes; Jenihhin, Maksim; Tšepurov, Anton28th Norchip Conference : Tampere, Finland, 15-16 November 2010 : conference program and papers2010 / [4] p. : ill http://dx.doi.org/10.1109/NORCHIP.2010.5669486

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344

book article

High-level fault diagnosis in RISC processors with Implementation-Independent Functional TestOyeniran, Adeboye Stephen; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Nicosia, Cyprus : 04-06 July 20222022 / p. 32-37 https://doi.org/10.1109/ISVLSI54635.2022.00019

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345

book article

High-level functional test generation for microprocessor modulesOyeniran, Adeboye Stephen; Ubar, Raimund-JohannesProceedings of 26th International Conference Mixed Design of Integrated Circuits and Systems : MIXDES 2019 : Rzeszów, Poland, June 27 - 29, 20192019 / p. 356-361 : ill https://doi.org/10.23919/MIXDES.2019.8787131

book article

346

journal article

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

journal article

347

dissertation

High-level implementation-independent software-based self-test for RISC type microprocessors = Mikroprotsessorite tarkvarapõhine implementatsioonist mittesõltuv funktsionaalne enesekontrollOyeniran, Adeboye Stephen2020 https://digikogu.taltech.ee/et/Item/08a75fbb-3f71-4fe4-b3d0-3f37a9a5f36d

dissertation

348

book article

High-level modeling and testing of multiple control faults in digital systemsJasnetski, Artjom; Oyeniran, Adeboye Stephen; Tšertov, Anton; Schölzel, Mario; Ubar, Raimund-JohannesFormal proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 20-22, 2016, Košice, Slovakia2016 / [6] p. : ill http://dx.doi.org/10.1109/DDECS.2016.7482445

book article

349

book article

High-level path activation technique to speed up sequential circuit test generationRaik, Jaan; Ubar, Raimund-JohannesEuropean Test Workshop 1999 : proceedings, May 25-28, 1999, Constance, Germany1999 / p. 84-89 : ill

book article

350

book article

High-level synthesis and test in the MOSCITO-based virtual laboratorySchneider, Andre; Diener, Karl-Heinz; Jervan, Gert; Peng, Z.; Raik, Jaan; Ubar, Raimund-Johannes; Hollstein, Thomas; Glesner, M.BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 287-290 : ill

book article

Ubar, Raimund-Johannes (TTÜ author)

types of item

CV 63

author 57

name of the person 28

subject term 1