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register transfer and gate level simulation (keyword)
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book article
Laboratory framework TEAM for investigating the dependability issues of microprocessor systems
Jasnetski, Artjom
;
Tšertov, Anton
;
Ubar, Raimund-Johannes
;
Kruus, Helena
10th European Workshop on Microelectronics Education : EWME 2014 : May 14-16, 2014, Tallinn, Estonia
2014
/
p. 80-83 : ill
book article
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keyword
29
1.
register transfer and gate level simulation
2.
gate and register transfer levels
3.
Register Transfer Level - RTL
4.
register transfer level modeling decision diagams
5.
register-transfer level
6.
gate-level analysis
7.
gate-level circuit abstraction
8.
gate-level netlist
9.
high-level fault simulation
10.
system level simulation
11.
diffusion (mass transfer, heat transfer)
12.
logic level and high level BDDs
13.
Swedish Cancer Register
14.
Field Programmable Gate Array (FPGA)
15.
field programmable gate arrays
16.
field-programmable gate array
17.
Field-Programmable Gate Array (FPGA)
18.
field-programmable gate arrays
19.
field-programmable gate arrays (FPGA)
20.
FPGA (field-programmable gate array)
21.
GaTe
22.
gate delay
23.
gate driver
24.
Gate Injection Transistor (GIT)
25.
Golden gate assembly
26.
insulated gate bipolar transistors
27.
insulated gate-commutated thyristors
28.
NBTI-critical gate
29.
Opal Kelly field programmable gate array (FPGA)
subject term
1
1.
Safety Gate
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