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gate-level analysis (keyword)
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1
journal article EST
/
journal article ENG
Fast identification of true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
;
Jürimägi, Lembit
Microelectronics reliability
2018
/
p. 252-261 : ill
https://doi.org/10.1016/j.microrel.2017.11.027
Journal metrics at Scopus
Article at Scopus
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Article at WOS
journal article EST
/
journal article ENG
2
book article
Hierarchical timing-critical paths analysis in sequential circuits
Jürimägi, Lembit
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
;
Raik, Jaan
;
Devadze, Sergei
;
Kostin, Sergei
2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018) : 2 – 4 July 2018, Spain
2018
/
6 p. : ill
https://doi.org/10.1109/PATMOS.2018.8464176
book article
3
book article
A scalable technique to identify true critical paths in sequential circuits
Ubar, Raimund-Johannes
;
Kostin, Sergei
;
Jenihhin, Maksim
;
Raik, Jaan
Proceedings 2017 IEEE 20th International Symposium on Design and Diagnotics of Electronic Circuit & Systems(DDECS) : April 19-21, 2017, Dresden, Germany
2017
/
p. 152-157 : ill
https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7934553
book article
Number of records 3, displaying
1 - 3
keyword
151
1.
gate-level analysis
2.
gate-level circuit abstraction
3.
gate-level netlist
4.
register transfer and gate level simulation
5.
hierarchical two-level analysis
6.
system-level analysis
7.
logic level and high level BDDs
8.
Field Programmable Gate Array (FPGA)
9.
field programmable gate arrays
10.
field-programmable gate array
11.
Field-Programmable Gate Array (FPGA)
12.
field-programmable gate arrays
13.
field-programmable gate arrays (FPGA)
14.
FPGA (field-programmable gate array)
15.
GaTe
16.
gate and register transfer levels
17.
gate delay
18.
gate driver
19.
Gate Injection Transistor (GIT)
20.
Golden gate assembly
21.
insulated gate bipolar transistors
22.
insulated gate-commutated thyristors
23.
NBTI-critical gate
24.
Opal Kelly field programmable gate array (FPGA)
25.
absolute sea level
26.
airport level of service
27.
arousal level
28.
assurance level
29.
behaviour level test generation
30.
bi-level optimization
31.
CO2 level in classrooms
32.
CO2 level in classrooms and kindergartens
33.
confidence level
34.
country-level logistics
35.
Cross-level Modeling of Faults in Digital Systems
36.
customer compatibility level
37.
deep level
38.
deep level traps
39.
determination of the CO2 level
40.
determining the level of creatine
41.
digitalisation level
42.
distribution-level phasor measurement units (D-PMUs)
43.
exposure level
44.
extreme penetration level of non synchronous generation
45.
extreme water level
46.
graduate level
47.
Hierarchical Multi-level Test Generation
48.
high level DD (HLDD)
49.
high level synthesis
50.
high-level control fault model
51.
high-level control faults
52.
high-level decision diagram
53.
high-level decision diagrams
54.
high-level decision diagrams (HLDD) synthesis
55.
High-level Decision Diagrams for Modeling Digital Systems
56.
high-level expert group on AI
57.
high-level fault coverage
58.
high-level fault model
59.
high-level fault simulation
60.
high-level functional fault model
61.
high-level synthesis
62.
High-Level Synthesis (HLS)
63.
high-level synthesis for test
64.
high-level test data generation
65.
improvement of safety level at enterprises
66.
improvement of safety level at SMEs
67.
level control
68.
level crossing
69.
level set
70.
level(s) methodology
71.
level-crossing ADC
72.
level-crossing analog-to-digital converters
73.
level-crossing analogue-to-digital converters (ADC)
74.
logic level
75.
lower trophic level models
76.
low-level control system transportation
77.
low-level fault redundancy
78.
low-level radiation
79.
Low-level RF EMF
80.
macro-level industry influences
81.
mean sea level
82.
module level power electronics (MLPE)
83.
module-level power electronics (MLPE)
84.
multi-level governance
85.
multi-level inverter
86.
multi-level modeling
87.
multi-level perspective
88.
multi-level perspective of sustainability transitions
89.
multi-level selection and processing environment
90.
operational level (OL)
91.
Price level
92.
Process/Product Sigma Performance Level (PSPL)
93.
PV module level power electronics
94.
Register Transfer Level - RTL
95.
register transfer level modeling decision diagams
96.
register-transfer level
97.
relative sea level
98.
relative sea level changes
99.
relative sea-level change
100.
RH level
101.
school-level policies
102.
sea level
103.
sea level forecasting
104.
sea level rise
105.
sea level series
106.
sea level trend
107.
sea level: variations and mean
108.
sea-level
109.
sea-level changes
110.
sea-level equation
111.
Sea-level indicator
112.
sea-level prediction
113.
sea-level rise
114.
sea-level trend
115.
service-level agreements
116.
seven-level multilevel
117.
Sigma performance level
118.
skin conductance level
119.
software level TMR
120.
steel-level bureaucracy
121.
strategic level decision makers
122.
system level
123.
system level hazards
124.
system level test
125.
system planning level
126.
system-level evaluation
127.
task-level uninterrupted presence
128.
three-level
129.
three-level converter
130.
three-level inverter
131.
three-level neutral-point-clamped inverter
132.
three-level NPC inverter
133.
three-level T-type
134.
three-level T-type inverter
135.
three-level T-type quasi-impedance-source inverter (3L-T-type qZSI)
136.
three-level voltage inverter
137.
Tool Confidence Level
138.
top-level domain
139.
transaction-level modeling
140.
treatment level
141.
two-level inverter
142.
undergraduate level
143.
university level informatics education
144.
water level
145.
water level fluctuation
146.
water level measurements
147.
water level reconstruction
148.
water-level changes
149.
voltage level
150.
voltage level optimisation
151.
3-level T-type inverter
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