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book article
Accurate NBTI-induced gate delay modeling based on intensive SPICE simulations
Kostin, Sergei
;
Raik, Jaan
;
Ubar, Raimund-Johannes
;
Jenihhin, Maksim
MEDIAN Finale : Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale : November 10-11, 2015, Tallinn, Estonia
2015
/
p. 21-26 : ill
book article
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keyword
44
1.
gate delay
2.
Field Programmable Gate Array (FPGA)
3.
field programmable gate arrays
4.
field-programmable gate array
5.
Field-Programmable Gate Array (FPGA)
6.
field-programmable gate arrays
7.
field-programmable gate arrays (FPGA)
8.
FPGA (field-programmable gate array)
9.
GaTe
10.
gate and register transfer levels
11.
gate driver
12.
Gate Injection Transistor (GIT)
13.
gate-level analysis
14.
gate-level circuit abstraction
15.
gate-level netlist
16.
Golden gate assembly
17.
insulated gate bipolar transistors
18.
insulated gate-commutated thyristors
19.
NBTI-critical gate
20.
Opal Kelly field programmable gate array (FPGA)
21.
register transfer and gate level simulation
22.
communication delay
23.
communication delay time
24.
delay
25.
delay control systems
26.
delay monad
27.
Delay systems
28.
delay-aware optimization
29.
digital delay
30.
ETE Delay
31.
fractional delay differential equations
32.
interlayer delay
33.
interval time delay
34.
NBTI-induced path delay estimation
35.
non-robust and functional sensitization of delay faults
36.
Power Delay Product (PDP)
37.
propagation delay
38.
service delay
39.
thermal delay
40.
time delay
41.
time delay systems
42.
time-delay renewable power systems
43.
time-delay systems
44.
transition delay faults
subject term
1
1.
Safety Gate
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