Otsing - TalTech teadusportaal

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76

artikkel kogumikus

Register-transfer level deductive fault simulation using decision diagramsReinsalu, Uljana; Raik, Jaan; Ubar, Raimund-JohannesBEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia2010 / p. 193-196 : ill

artikkel kogumikus

77

artikkel kogumikus

Remarks on different decision diagramsStankovic, Radomir S.; Ubar, Raimund-Johannes; Astola, JaakkoProceedings of the Reed-Muller 2011 Workshop : May 25-26, 2011, Tuusula, Finland2011 / p. 99-110 : ill

artikkel kogumikus

78

artikkel kogumikus

Sequential circuit test generation using decision diagram modelsRaik, Jaan; Ubar, Raimund-JohannesDesign, Automation and Test in Europe : DATE : Conference and Exhibition 1999 : Munich, Germany, March 9-12, 1999 : proceedings1999 / p. 736-740: ill https://www.cs.york.ac.uk/rts/docs/SIGDA-Compendium-1994-2004/papers/1999/date99/pdffiles/11e_1.pdf

artikkel kogumikus

79

artikkel kogumikus

Simulation-based verification with APRICOT framework using high-level decision diagramsJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesEast-West Design & Test Symposium : Moscow, September 18-21, 20092009 / p. 13-16 : ill

artikkel kogumikus

80

artikkel kogumikus

SoC and board modeling for processor-centric board testingTšertov, Anton; Ubar, Raimund-Johannes; Jutman, Artur; Devadze, Sergei14th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : DSD 2011 : 31 August - 2 September 2011, Oulu, Finland : proceedings2011 / p. 575-582 : ill https://ieeexplore.ieee.org/document/6037463

artikkel kogumikus

81

artikkel kogumikus

Software-based self-test generation for microprocessors with high-level decision diagramsUbar, Raimund-Johannes; Tšertov, Anton; Jasnetski, Artjom; Brik, MarinaLATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 20142014 / [6] p. : ill

artikkel kogumikus

82

artikkel ajakirjas EST / artikkel ajakirjas ENG

Software-based self-test generation for microprocessors with high-level decision diagramsJasnetski, Artjom; Ubar, Raimund-Johannes; Tšertov, Anton; Brik, MarinaProceedings of the Estonian Academy of Sciences2014 / p. 48-61 : ill https://artiklid.elnet.ee/record=b2665215*est https://doi.org/10.3176/proc.2014.1.08 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

artikkel ajakirjas EST / artikkel ajakirjas ENG

83

raamat

Software-based self-test with decision diagrams for microprocessorsUbar, Raimund-Johannes; Jasnetski, Artjom; Tšertov, Anton; Oyeniran, Adeboye Stephen2018

raamat

84

raamat

Structural decision diagrams in digital test : theory and applicationsUbar, Raimund-Johannes; Raik, Jaan; Jenihhin, Maksim; Jutman, Artur2024 https://doi.org/10.1007/978-3-031-44734-1 https://www.ester.ee/record=b5734441*est

raamat

85

artikkel kogumikus

Structural fault collapsing by superposition of BDDs for test generation in digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, ArturProceedings of the Eleventh International Symposium on Quality Electronic Design ISQED 2010 : March 22-24, 2010 San Jose, California USA2010 / p. 250-257 : ill https://ieeexplore.ieee.org/document/5450451

artikkel kogumikus

86

artikkel kogumikus

Structurally synthesized binary decision diagramsJutman, Artur; Peder, Ahti; Raik, Jaan; Tombak, Mati; Ubar, Raimund-JohannesBoolean Problems : 6th International Workshop : September 23-24, 2004, Freiberg2004 / p. 271-278 : ill

artikkel kogumikus

87

artikkel kogumikus

Structurally synthesized multiple input BDDs for simulation of digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, Artur16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009 : Yasmine Hammamet, Tunesia, 13-19 December, 20092009 / p. 451-454 : ill http://dx.doi.org/10.1109/ICECS.2009.5410895

artikkel kogumikus

88

artikkel ajakirjas

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generationLeveugle, R.; Ubar, Raimund-JohannesElectron technology1999 / 3, p. 282-287 : ill

artikkel ajakirjas

89

artikkel kogumikus

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generationLeveugle, R.; Ubar, Raimund-JohannesProceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 19981998 / p. 353-358 https://hal.science/ccsd-00015077/

artikkel kogumikus

90

artikkel kogumikus

Synthesis of high-level decision diagrams for functional test pattern generationUbar, Raimund-Johannes; Raik, Jaan; Karputkin, Anton; Tombak, MatiProceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland, 25-27 June, 20092009 / p. 519-524 : ill

artikkel kogumikus

91

artikkel kogumikus

Teaching diagnostic modeling of digital systems with decision diagrams [Electronic resource]Ubar, Raimund-Johannes; Raik, Jaan; Mironov, Dmitri; Evartson, Teet; Orasson, Elmet; Aarna, Margit; Wuttke, Heinz-DietrichProceedings of 12th IASTED International Conference on Computers and Advanced Technology in Education - CATE 2009 : St.Thomas, US, November 22-24, 20092009 / p. 1-6. [CD-ROM]

artikkel kogumikus

92

artikkel kogumikus

Temporally extended high-level decision diagrams for PSL assertions simulationJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Ubar, Raimund-JohannesProceedings : Thirteenth IEEE European Test Symposium : ETS 2008 : 25-29 May 2008, Verbania, Italy2008 / p. 61-68 : ill https://ieeexplore.ieee.org/document/4556029

artikkel kogumikus

93

artikkel kogumikus

Testability calculation for digital circuits with decision diagramsUbar, Raimund-Johannes3rd IEEE Latin American Test Workshop : LATW'02, Montevideu, Uruguay, February 10-13, 2002 : digest of papers2002 / p. 137-143 : ill https://dblp.org/rec/conf/latw/Ubar02.html

artikkel kogumikus

94

artikkel kogumikus

Testability guided hierarchical test generation with decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Nõmmeots, Tanel20th IEEE NORCHIP Conference : Copenhagen, Denmark, November 11-12, 20022002 / p. 265-271 https://www.semanticscholar.org/paper/Testability-Guided-Hierarchical-Test-Generation-Ubar-Raik/c6301ac35d003c92f3867f26e2e75b87e1ad9b47

artikkel kogumikus

95

artikkel kogumikus

Timing simulation of digital circuits with binary decision diagramsUbar, Raimund-Johannes; Jutman, Artur; Peng, Z.Design, Automation and Test in Europe : Conference and Exhibition 2001 : Munich, Germany, March 13-16, 2001 : proceedings2001 / p. 460-466 : ill https://ieeexplore.ieee.org/document/915063

artikkel kogumikus

96

artikkel kogumikus

True path tracing in structurally synthesized BDDs for testability analysis of digital circuitsUbar, Raimund-Johannes; Jürimägi, Lembit; Oyeniran, Adeboye Stephen; Jenihhin, MaksimEuromicro Conference on Digital System Design : DSD 2019 : 28 - 30 August 2019 Kallithea, Chalkidiki, Greece : proceedings2019 / p. 492-499 : ill https://doi.org/10.1109/DSD.2019.00077

artikkel kogumikus

97

artikkel kogumikus

Using test pattern generation tool decider in hardware verificationViilukas, Taavi; Raik, JaanInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 166-169 : ill

artikkel kogumikus

98

artikkel kogumikus

Vector decision diagrams for simulation of digital systemsUbar, Raimund-Johannes; Morawiec, Adam; Raik, JaanDDECS'20002000 / p. 44-51

artikkel kogumikus

99

raamat

Verification and error correction on High-Level Decision DiagramsKarputkin, Anton2013

raamat

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