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176

artikkel kogumikus

Reseeding using compaction of pre-generated LFSR sub-sequencesJutman, Artur; Aleksejev, Igor; Raik, Jaan; Ubar, Raimund-JohannesICECS 2008 : The 15th IEEE International Conference on Electronics, Circuits and Systems : Malta2008 / p. 1290-1295 : ill http://dx.doi.org/10.1109/ICECS.2008.4675096

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177

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Re-using chip level DFT at board levelGu, Xinli; Jutman, ArturProceedings : 2012 17th IEEE European Test Symposium (ETS) : May 28th–June 1st, 2012, Annecy, France2012 / 1 p https://www.academia.edu/25351525/Re_using_chip_level_DFT_at_board_level

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178

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Reusing verification assertions as security checkers for Hardware Trojan detectionEslami, Mohammad; Ghasempouri, Tara; Pagliarini, Samuel Nascimento2022 23rd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA : 06-07 April 20222022 / p. 1-6 : ill https://doi.org/10.1109/ISQED54688.2022.9806292

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Seotud publikatsioonid 1

On the use of defensive schemes for hardware security = Kaitseskeemid riistvara turvalisuse tagamiseks

179

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SCARF : securing chips with a robust framework against fabrication-time hardware trojansEslami, Mohammad; Ghasempouri, Tara; Pagliarini, Samuel NascimentoIEEE Transactions on Computers2024 / p. 2761-2775 https://doi.org/10.1109/TC.2024.3449082 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

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Seotud publikatsioonid 1

SCARF : securing chips with a robust framework against fabrication-time hardware Trojans : preprint

180

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Second IEEE East-West Design and Test WorkshopHahanov, Vladimir; Ubar, Raimund-JohannesIEEE journal of design & test of computers2004 / p. 594

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181

dissertatsioon

Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline sünteesPerez, Tiago Diadami2023 https://doi.org/10.23658/taltech.4/2023 https://digikogu.taltech.ee/et/Item/440f41fd-0950-4b5c-8e47-4f75a754cdae https://www.ester.ee/record=b5536743*est

dissertatsioon

Seotud publikatsioonid 6

182

artikkel ajalehes

Sensortehnoloogia põhised kiibid on Eesti võimalus : Alar Kuusik: „Ootan väga, et ühiskonnas tuleks tagasi vastuvõtlikkus uutele, ka radikaalsetele lahendustele ja reformidele.“Kuusik, Alarsirp.ee2025 https://www.sirp.ee/sensortehnoloogia-pohised-kiibid-on-eesti-voimalus/

artikkel ajalehes

183

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Shift register based TPG for at-speed interconnect BISTJutman, ArturMIEL 2004 : 24th International Conference on Microelectronics : Niš, Serbia and Montenegro, 16-19 May 2004 : proceedings. Volume 22004 / p. 751-754 : ill https://ieeexplore.ieee.org/document/1314941?signout=success

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184

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Side-channel attacks on triple modular redundancy schemesAlmeida, Felipe; Aksoy, Levent; Raik, Jaan; Pagliarini, Samuel Nascimento2021 IEEE 30th Asian Test Symposium ATS 2021 : proceedings2021 / p. 79-84 : ill https://doi.org/10.1109/ATS52891.2021.00026 Conference Proceedings at Scopus Article at Scopus Article at WOS

artikkel kogumikus EST / artikkel kogumikus ENG

185

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A side-channel hardware trojan in 65nm CMOS with 2μW precision and multi-bit leakage capabilityPerez, Tiago Diadami; Pagliarini, Samuel Nascimento2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) : 17-20 January 2022 : Taipei, Taiwan2022 / p. 9-10 : ill https://doi.org/10.1109/ASP-DAC52403.2022.9712490

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Seotud publikatsioonid 1

Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline süntees

186

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Side-channel Trojan insertion - a practical foundry-side attack via ECOPerez, Tiago Diadami; Imran, Malik; Vaz, Pablo; Pagliarini, Samuel Nascimento2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, May 22-28, 2021 : proceedings2021 / 5 p. : ill https://doi.org/10.1109/ISCAS51556.2021.9401481 Conference Proceedings at Scopus Article at Scopus Article at WOS

artikkel kogumikus EST / artikkel kogumikus ENG

Seotud publikatsioonid 1

Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline süntees

187

artikkel ajakirjas

Silicon integrated circuit fabrication process modeling and simulationRang, Toomas; Tarnay, K.; Mizsei, JanosPeriodica polytechnica. Electrical engineering = Электротехника1980 / p. 109-113 https://www.ester.ee/record=b1198855*est

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188

artikkel kogumikus

A simulation framework for 3-dimension networks-on-chip with different vertical channel density configurationsYing, Haoyuan; Jaiswal, Ashok; Abd El Ghany, Mohamed A; Hollstein, Thomas; Hofmann, KlausProceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 18-20, 2012 Tallinn, Estonia2012 / p. 83-88 : ill

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189

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Split-chip design to prevent IP reverse engineeringPagliarini, Samuel Nascimento; Sweeney, Joseph; Mai, Ken; Blanton, Shawn; Mitra, Subhasish; Pileggi, LarryIEEE Design and Test2020 / p. 109-118 https://doi.org/10.1109/MDAT.2020.3033255 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

artikkel ajakirjas EST / artikkel ajakirjas ENG

190

artikkel kogumikus

State assignment for CMOS implementation of low power FSM networksZaugarov, Viktor; Kasirova, Lilia; Tveretina, OlgaMixed Design of Integrated Circuits and Systems : education of computer aided design of modern ICs and devices : 3rd Advanced Training Course, Lodz, Poland, 30 May - 1 June 19961996 / p. 195-198: ill

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191

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Steady state analysis of an output signal based combination of two NLMS adaptive filtersTrump, Tõnu17th European Signal Processing Conference (EUSIPCO 2009) : 24-28 August 20092009 / p. 1720-1724 https://ieeexplore.ieee.org/document/7077570

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192

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Steady state analysis of the galvanically isolated DC/DC converter with a commutating LC filter [Electronic resource]Zakis, Janis; Vinnikov, Dmitri; Rankis, Ivars2012 IEEE International Conference on Industrial Technology : proceedings CD2012 / p. 838-843 : ill [CD-ROM] https://ieeexplore.ieee.org/document/6210041

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193

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Structurally synthesized multiple input BDDs for simulation of digital circuitsUbar, Raimund-Johannes; Mironov, Dmitri; Raik, Jaan; Jutman, Artur16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009 : Yasmine Hammamet, Tunesia, 13-19 December, 20092009 / p. 451-454 : ill http://dx.doi.org/10.1109/ICECS.2009.5410895

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194

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A survey on split manufacturing : attacks, defenses, and challengesPerez, Tiago Diadami; Pagliarini, Samuel NascimentoIEEE Access2020 / p. 184013-184035 https://doi.org/10.1109/ACCESS.2020.3029339 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

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Seotud publikatsioonid 1

Security-aware physical synthesis of integrated circuits = Integraallülituste turvateadlik füüsiline süntees

195

raamat

Süvatehnoloogiate alternatiivsed arengutrajektoorid ja nende tähendus Eestile : lõpparuanneKoppel, Kaupo; Kuusik, Alar; Arrak, Kadri; Raik, Jaan; Niidu, Allan; Kõks, Kerttu-Liis; Lahtvee, Petri-Jaan2023 https://media.voog.com/0000/0037/5345/files

raamat

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Symmetry in the narrow sense: on the linearity and time-invariance of DQ0 modelsSegev, Elior; Ofir, Ron; Belikov, Juri; Levron, YoashIEEE Transactions on Power Systems2023 / p. 1751-1754 https://doi.org/10.1109/TPWRS.2022.3229873 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

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197

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Synthesis of multiple fault oriented test groups from single fault test sets [Electronic resource]Ubar, Raimund-Johannes; Kostin, Sergei; Raik, Jaan2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) : 26-28 March 2013, Abu Dhabi, UAE2013 / p. 36-41 : ill [CD-ROM]

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198

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Synthesis of sequential circuits with dynamic power managementLensen, Harri; Kruus, Margus; Sudnitsõn, AleksanderProc. of 42nd International Scientific Conference of Riga Technical University : RTUCET'012001 / p. 81-86

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199

artikkel ajakirjas

Synthesis of sequential circuits with dynamic power managementLensen, Harri; Kruus, Margus; Sudnitsõn, AleksanderScientific proceedings of Riga Technical University. 7.serija, Telecommunications and electronics2001 / p. 81-86

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200

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System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memoryPuttaswamy, Kiran; Choi, Kyu-Won; Park, Jun Cheol; Mooney III, Vincent J.; Chatterjee, Abhijit; Ellervee, PeeterISSS'02, October 2-4, 2002, Kyoto, Japan2002 / p. 225-230 : ill https://ieeexplore.ieee.org/document/1227182

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