Hybrid BIST time minimization for core-based systems with STUMPS architecture
statement of authorship
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
source
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings
location of publication
Los Alamitos
publisher
year of publication
pages
p. 225-232 : ill
conference name, date
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 3-5 November, 2003
conference location
Boston, Massachusetts, USA
ISSN
1550-5774
ISBN
0-7695-2042-1
notes
Bibliogr.: 15 ref
language
inglise
Jervan, G., Eles, P., Peng, Z., Ubar, R.-J., Jenihhin, M. Hybrid BIST time minimization for core-based systems with STUMPS architecture // 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings. Los Alamitos : IEEE Computer Society, 2003. p. 225-232 : ill.