Hybrid BIST time minimization for core-based systems with STUMPS architecture
vastutusandmed
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
allikas
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings
ilmumiskoht
Los Alamitos
kirjastus/väljaandja
ilmumisaasta
leheküljed
p. 225-232 : ill
konverentsi nimetus, aeg
18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 3-5 November, 2003
konverentsi toimumispaik
Boston, Massachusetts, USA
ISSN
1550-5774
ISBN
0-7695-2042-1
märkused
Bibliogr.: 15 ref
keel
inglise
Jervan, G., Eles, P., Peng, Z., Ubar, R.-J., Jenihhin, M. Hybrid BIST time minimization for core-based systems with STUMPS architecture // 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings. Los Alamitos : IEEE Computer Society, 2003. p. 225-232 : ill. https://ieeexplore.ieee.org/document/1250116