Searching - TalTech Research Portal

display

sort

1

book article

Abstraction of clock interface for conversion of RTL VHDL to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, Jaan2014 IEEE International Advance Computing Conference (IACC) : February 21-22, 2014, Gurgaon, India2014 / p. 50-55 : ill

book article

2

dissertation

Comprehensive abstraction of VHDL RTL cores to ESL SystemC = Register-siirde taseme VHDL kirjelduste kompleksne abstraheerimine süsteemitaseme SystemC mudeliteksAbrar, Syed Saif2016 http://www.ester.ee/record=b4564850*est

dissertation

3

book article

Extensible open-source framework for translating RTL VHDL IP cores to SystemCSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 8-10, 2013, Karlovy Vary, Czech Republic2013 / p. 112-115

book article

4

book article

FSMD RTL design manipulation for clock interface abstractionAbrar, Syed Saif; Jenihhin, Maksim; Raik, Jaan2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 10-13 August 2015, Kerala, India2015 / p. 463-468 : ill http://dx.doi.org/10.1109/ICACCI.2015.7275652

book article

5

book article

Optimization methodologies for Cycle-Accurate SystemC models converted from RTL VHDLSaif Abrar, Syed; Jenihhin, Maksim; Raik, JaanIP-SoC 2013 : IP embbeded system conference and exhibition : Grenoble, France, November 6-7, 20132013

book article

6

book article

Performance analysis of cosimulating processor core in VHDL and SystemCSaif Abrar, Syed; Shyam Kiran A.; Jenihhin, Maksim; Raik, Jaan; Babu, C.Proceedings of the 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI) : 22–25 August 2013, Mysore, India2013 / p. 563-568 : ill

book article

7

book article

SystemC-based loose models : RTL abstraction for design understandingAbrar, Syed Saif; Jenihhin, Maksim; Raik, JaanWorkshop on Design Automation for Understanding Hardware Designs DUHDe 2015 : Grenoble, March 13, 20152015 / p. 1-6

book article

8

book article

SystemC-based loose models for simulation speed-up by abstraction of RTL IP coresAbrar, Syed Saif; Jenihhin, Maksim; Raik, Jaan2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings2015 / p. 71-74 : ill http://dx.doi.org/10.1109/DDECS.2015.39

book article

SystemC (programmeerimiskeel) (subject term)

types of item

subject term 38

keyword 1