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High-level combined deterministic and pseudo-exhuastive test generation for RISC processors

author
Oyeniran, Adeboye Stephen
Ubar, Raimund-Johannes
Jenihhin, Maksim
Gürsoy, Cemil Cem
Raik, Jaan
statement of authorship
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
source
2019 IEEE European Test Symposium (ETS) : proceedings
location of publication
Danvers
publisher
IEEE
year of publication
2019
pages
6 p. : ill
conference name, date
2019 IEEE European Test Symposium ETS 2019, May 27 - 31, 2019
conference location
Baden Baden, Germany
url
https://doi.org/10.1109/ETS.2019.8791526
subject term
mikroprotsessorid
testimine
keyword
RISC processors
high-level fault model
highlevel test generation
deterministic and pseudo-exhaustive tests
control and data path tests
ISSN
1558-1780
1530-1877
ISBN
978-1-7281-1173-5
978-1-7281-1174-2
notes
Bibliogr.: 31 ref
TTÜ department
arvutisüsteemide instituut
language
inglise
Uurimisrühm
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems
Oyeniran, A. S., Ubar, R., Jenihhin, M., ; Gürsoy, C. C., Raik, J. High-level combined deterministic and pseudo-exhuastive test generation for RISC processors // 2019 IEEE European Test Symposium (ETS) : proceedings. Danvers : IEEE, 2019. 6 p. : ill. https://doi.org/10.1109/ETS.2019.8791526