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Logic IP for low-cost IC design in advanced CMOS nodes

author
statement of authorship
Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Larry Pileggi
source
publisher
journal volume number month
vol. 28, no. 2
year of publication
pages
p. 585-595
url
ISSN
1063-8210
557-9999
notes
Bibliogr.: 29 ref
language
inglise
subject term
keyword
Pins
Routing
Layout
Computer architecture
Microprocessors
Libraries
CMOS scaling
digital integrated circuit (IC) design
layout patterns
logic cell library
routing closure
Reserch Group
Centre for hardware security
Isgenc, M.M., Martins, M.G.A., Zackriya, M., Pagliarini, S.N., Pileggi, L. Logic IP for low-cost IC design in advanced CMOS nodes // IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2020) vol. 28, no. 2, p. 585-595. https://doi.org//10.1109/TVLSI.2019.2942825