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Translating Common Security Assertions Across Processor Designs : A RISC-V Case Study

author
statement of authorship
Sharjeel Imtiaz, Uljana Reinsalu, Tara Ghasempouri
source
2025 IEEE International Symposium on Circuits and Systems (ISCAS)
publisher
year of publication
pages
5 p
conference name, date
IEEE International Symposium on Circuits and Systems (ISCAS), 25-28 May 2025
conference location
London, United Kingdom
url
ISSN
2158-1525
ISBN
9798350356830
scientific publication
teaduspublikatsioon
TalTech department
language
Estonian,English
subject term
keyword
Security Verification
Security Assertion
RISC-V Processor
Hardware Trojan
Register-Transfer Level (RTL)
Imtiaz, S., Reinsalu, U., Ghasempouri, T. Translating Common Security Assertions Across Processor Designs : A RISC-V Case Study // 2025 IEEE International Symposium on Circuits and Systems (ISCAS). : IEEE, 2025. 5 p. https://doi.org/10.1109/ISCAS56072.2025.11043977