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Processor vulnerability detection with the aid of assertions : RISC-V case study

author
statement of authorship
Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri
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p. 1-8 : ill
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Bibliogr.: 36 ref
scientific publication
teaduspublikatsioon
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inglise
subject term
subject of form
keyword
Automatic Security Verification
RISC-V Security Verification
Security Assertion Mining
Data Mining
Heidari Iman, M.R., Ahmadi-Pour, S., Drechsler, R., Ghasempouri, T. Processor vulnerability detection with the aid of assertions : RISC-V case study // techrxiv.org (2024), p. 1-8 : ill. https://doi.org/10.36227/techrxiv.172101134.45466090/v1