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book article
SCAAT: Secure cache alternative address table for mitigating cache logical side-channel attacks
Shalabi, Ameer
;
Ghasempouri, Tara
;
Ellervee, Peeter
;
Raik, Jaan
2020 23rd Euromicro Conference on Digital System Design (DSD), 26-28 August 2020, Kranj, Slovenia
2020
/
art, 20035366, p. 213−217
https://doi.org/10.1109/DSD51259.2020.00043
book article
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keyword
41
1.
cache memory
2.
cache
3.
cache attacks
4.
cache security
5.
Cache Side-Channel Attacks
6.
cache storage
7.
cache vulnerability analysis
8.
instruction cache
9.
activation memory
10.
Digital Object Memory
11.
in-memory databases
12.
learning and memory
13.
long short term memory
14.
long short -term memory (LSTM)
15.
long short-term memory
16.
long short-term memory (LSTM)
17.
Long Short-Term Memory Networks (LSTMs)
18.
long-short term memory
19.
long-short-term memory (LSTM)
20.
material with memory
21.
memory
22.
memory architecture
23.
memory bottleneck
24.
memory effect
25.
memory efficiency
26.
memory interconnect test
27.
memory kernels
28.
memory management
29.
memory network
30.
memory overhead
31.
memory systems
32.
memory testing
33.
memory-induced resonance
34.
National memory
35.
non-volatile memory
36.
processing-in-memory
37.
random access memory
38.
relaxed memory
39.
shape memory alloy
40.
Shape memory alloys
41.
shape memory efect
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