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Assertion checking with PSL and high-level decision diagrams (title)
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book article
Assertion checking with PSL and high-level decision diagrams
Jenihhin, Maksim
;
Raik, Jaan
;
Tšepurov, Anton
;
Ubar, Raimund-Johannes
Digest of papers IEEE 8th Workshop on RTL and High Level Testing : WRTLT'07 : October 12-13, 2007, Beijing, China
2007
/
p. 105-110 : ill
https://pld.ttu.ee/~maksim/phd_papers/%5B12%5D%20wrtlt%2707.pdf
book article
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keyword
28
1.
high-level decision diagrams
2.
high-level decision diagrams (HLDD) synthesis
3.
High-level Decision Diagrams for Modeling Digital Systems
4.
high-level decision diagram
5.
logic level and high level BDDs
6.
verification, assertion-based verification, automatic assertion mining, data mining, association rule mining
7.
Binary Decision Diagrams
8.
binary decision diagrams (BDD)
9.
decision diagrams
10.
highlevel decision diagrams
11.
shared structurally synthesized Binary Decision Diagrams
12.
Structural Decision Diagrams for Modeling Digital Circuits
13.
register transfer level modeling decision diagams
14.
strategic level decision makers
15.
high level DD (HLDD)
16.
high level of security
17.
high level synthesis
18.
high-level control fault model
19.
high-level control faults
20.
high-level expert group on AI
21.
high-level fault coverage
22.
high-level fault model
23.
high-level fault simulation
24.
high-level functional fault model
25.
high-level synthesis
26.
High-Level Synthesis (HLS)
27.
high-level synthesis for test
28.
high-level test data generation
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