Searching - TalTech Research Portal

Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles

Research Groups

Help and information

Searching

high-level fault coverage (keyword)

—

—

—

—

Add criteria Advanced search filter

Clear

types of item

book ..

journal article ..

newspaper article ..

book article ..

dissertation ..

Open Access ..

Scientific publications ..

year

year of publication

Loading..

Loading..

TalTech department

Loading..

Loading..

Loading..

name of the person

Loading..

Loading..

Clear

Number of records 4
Look more.. (1/120)
Export

export all inquiry results (4)
Save TXT fail

print
Open for editing with marked entries my bookmarks

display

sort
1

journal article

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

journal article
2

book article

High-level test generation for processing elements in many-core systemsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Azad, Siavoosh Payandeh; Raik, Jaan12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2017), July 12-14, 2017, Madrid, Spain : proceedings2017 / 8 p. : ill http://dx.doi.org/10.1109/ReCoSoC.2017.8016156

book article
3

book article

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

book article
4

book article EST / book article ENG

On test generation for microprocessors for extended class of functional faultsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers2020 / p. 21-44 https://doi.org/10.1007/978-3-030-53273-4 Conference proceedings at Scopus Article at Scopus

book article EST / book article ENG

Number of records 4, displaying 1 - 4

1. high-level fault coverage
2. high-level control fault model
3. high-level fault model
4. high-level fault simulation
5. high-level functional fault model
6. fault coverage
7. logic level and high level BDDs
8. low-level fault redundancy
9. high level DD (HLDD)
10. high level of security
11. high level synthesis
12. high-level control faults
13. high-level decision diagram
14. high-level decision diagrams
15. high-level decision diagrams (HLDD) synthesis
16. High-level Decision Diagrams for Modeling Digital Systems
17. high-level expert group on AI
18. high-level synthesis
19. High-Level Synthesis (HLS)
20. high-level synthesis for test
21. high-level test data generation
22. High-Pressure High-Temperature Spark Plasma Sintering
23. code coverage
24. code-coverage
25. conceptual coverage
26. coverage
27. coverage factor
28. diagnostic coverage
29. gaps in coverage
30. insurance coverage
31. NB-IoT coverage
32. Security Coverage
33. stress coverage
34. test coverage
35. 5G coverage
36. asynchronous fault detection
37. automatic fault diagnosis
38. bearing fault diagnosis
39. bi-directional fault monitoring devices
40. conditional fault collapsing
41. control fault models
42. critical path fault tracing
43. cross-layer fault tolerance
44. cross-layered fault management
45. extended fault class
46. fault currents
47. fault analysis
48. fault analysis model
49. fault classification
50. fault classification
51. fault collapsing
52. fault compensation
53. fault current and voltage measurements
54. Fault current limite
55. fault current limiter
56. fault detection
57. fault detection and diagnoses
58. fault detection and diagnosis
59. fault diagnosis
60. fault diagnostic
61. fault diagnostic resolution
62. fault diagnostics
63. fault dignosis
64. fault effects
65. fault emulation
66. fault equivalence and dominance
67. fault handling
68. fault handling strategy
69. fault indicator
70. fault injection
71. Fault Injection Simulation
72. fault Interruption
73. fault localization
74. fault location
75. fault management
76. fault masking
77. fault modeling
78. fault models
79. fault monitoring
80. fault prediction
81. fault protection
82. fault redundancy
83. fault resilience
84. fault ride through
85. Fault ride through enhancement
86. fault signal
87. fault simulastion
88. fault simulation
89. fault simulation with critical path tracing
90. fault tolerance
91. fault tolerant
92. fault tolerant control
93. fault tolerant operation
94. fault tolerant router design
95. fault tolerant systems
96. fault tree analysis
97. fault-injection attack
98. fault-plane solution
99. fault-resilience
100. fault-resistant
101. fault-ride-through (FRT)
102. fault-tolerance
103. fault-tolerant
104. Fault-tolerant (FT) converters
105. fault-tolerant control
106. fault-tolerant converter
107. functional fault model
108. Katun fault
109. no fault found
110. No-Fault-Found
111. open circuit fault
112. Parallel Fault Simulation with Critical Path Backtracing
113. parallel fault-simulation
114. short circuit fault
115. spectrum-based fault localization
116. stacking fault
117. stuck-at fault model
118. test generation and fault diagnosis
119. transient fault mitigation
120. transmission lines fault

match

sort

Otsing
Valikud 0

year of publication

author

TalTech department

subject term

series

name of the person

keyword

TalTech Library

Akadeemia tee 1

13519

TalTech homepage TalTech Library homepage Digital Collection of TalTech Library Digiteek Repository

6203551

data@taltech.ee

TalTech Raamatukogu