Searching - TalTech Research Portal

Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles

Research Groups

Help and information

Searching

high-level fault coverage (keyword)

—

—

—

—

Add criteria Advanced search filter

Clear

types of item

book ..

journal article ..

newspaper article ..

book article ..

dissertation ..

Open Access ..

Scientific publication ..

year

year of publication

Loading..

Loading..

TTÜ department

Loading..

Loading..

Loading..

name of the person

Loading..

Loading..

Clear

Number of records 4
Look more.. (1/119)
Export

export all inquiry results (4)
Save TXT fail

Save PDF fail

print
Open for editing with marked entries my bookmarks

display

sort
1

journal article

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC ProcessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanJournal of electronic testing : theory and applications2020 / p. 87-103 https://doi.org/10.1007/s10836-020-05856-7

journal article
2

book article

High-level test generation for processing elements in many-core systemsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Azad, Siavoosh Payandeh; Raik, Jaan12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC2017), July 12-14, 2017, Madrid, Spain : proceedings2017 / 8 p. : ill http://dx.doi.org/10.1109/ReCoSoC.2017.8016156

book article
3

book article

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

book article
4

book article EST / book article ENG

On test generation for microprocessors for extended class of functional faultsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers2020 / p. 21-44 https://doi.org/10.1007/978-3-030-53273-4 Conference proceedings at Scopus Article at Scopus

book article EST / book article ENG

Number of records 4, displaying 1 - 4

1. high-level fault coverage
2. high-level control fault model
3. high-level fault model
4. high-level fault simulation
5. high-level functional fault model
6. fault coverage
7. logic level and high level BDDs
8. low-level fault redundancy
9. high level DD (HLDD)
10. high level synthesis
11. high-level control faults
12. high-level decision diagram
13. high-level decision diagrams
14. high-level decision diagrams (HLDD) synthesis
15. High-level Decision Diagrams for Modeling Digital Systems
16. high-level expert group on AI
17. high-level synthesis
18. High-Level Synthesis (HLS)
19. high-level synthesis for test
20. high-level test data generation
21. High-Pressure High-Temperature Spark Plasma Sintering
22. code coverage
23. code-coverage
24. conceptual coverage
25. coverage
26. coverage factor
27. diagnostic coverage
28. gaps in coverage
29. insurance coverage
30. NB-IoT coverage
31. Security Coverage
32. stress coverage
33. test coverage
34. 5G coverage
35. asynchronous fault detection
36. automatic fault diagnosis
37. bearing fault diagnosis
38. bi-directional fault monitoring devices
39. conditional fault collapsing
40. control fault models
41. critical path fault tracing
42. cross-layer fault tolerance
43. cross-layered fault management
44. extended fault class
45. fault currents
46. fault analysis
47. fault analysis model
48. fault classification
49. fault classification
50. fault collapsing
51. fault compensation
52. fault current and voltage measurements
53. Fault current limite
54. fault current limiter
55. fault detection
56. fault detection and diagnoses
57. fault detection and diagnosis
58. fault diagnosis
59. fault diagnostic
60. fault diagnostic resolution
61. fault diagnostics
62. fault dignosis
63. fault effects
64. fault emulation
65. fault equivalence and dominance
66. fault handling
67. fault handling strategy
68. fault indicator
69. fault injection
70. Fault Injection Simulation
71. fault Interruption
72. fault localization
73. fault location
74. fault management
75. fault masking
76. fault modeling
77. fault models
78. fault monitoring
79. fault prediction
80. fault protection
81. fault redundancy
82. fault resilience
83. fault ride through
84. Fault ride through enhancement
85. fault signal
86. fault simulastion
87. fault simulation
88. fault simulation with critical path tracing
89. fault tolerance
90. fault tolerant
91. fault tolerant control
92. fault tolerant operation
93. fault tolerant router design
94. fault tolerant systems
95. Fault Tree Analysis
96. fault-injection attack
97. fault-plane solution
98. fault-resilience
99. fault-resistant
100. fault-ride-through (FRT)
101. fault-tolerance
102. fault-tolerant
103. Fault-tolerant (FT) converters
104. fault-tolerant control
105. fault-tolerant converter
106. functional fault model
107. Katun fault
108. no fault found
109. No-Fault-Found
110. open circuit fault
111. Parallel Fault Simulation with Critical Path Backtracing
112. parallel fault-simulation
113. short circuit fault
114. spectrum-based fault localization
115. stacking fault
116. stuck-at fault model
117. test generation and fault diagnosis
118. transient fault mitigation
119. transmission lines fault

match

sort

Otsing
Valikud 0

year of publication

author

TTÜ department

subject term

series

name of the person

keyword

TalTech Library

Akadeemia tee 1

13519

TalTech homepage TalTech Library homepage Digital Collection of TalTech Library Digiteek Repository

6203551

data@taltech.ee

TalTech Raamatukogu