Searching - TalTech Research Portal

Publications
Profiles
Research Groups
Indexes
Help and information
Eesti keeles

Research Groups

Help and information

Searching

high-level functional fault model (keyword)

—

—

—

—

Add criteria Advanced search filter

Clear

types of item

book ..

journal article ..

newspaper article ..

book article ..

dissertation ..

Open Access ..

Scientific publication ..

year

year of publication

Loading..

Loading..

TTÜ department

Loading..

Loading..

Loading..

name of the person

Loading..

Loading..

Clear

Number of records 4
Look more.. (1/22)
Export

export all inquiry results (4)
Save TXT fail

Save PDF fail

print
Open for editing with marked entries my bookmarks

display

sort
1

book article

High-level fault diagnosis in RISC processors with Implementation-Independent Functional TestOyeniran, Adeboye Stephen; Jenihhin, Maksim; Raik, Jaan; Ubar, Raimund-Johannes2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) : Nicosia, Cyprus : 04-06 July 20222022 / p. 32-37 https://doi.org/10.1109/ISVLSI54635.2022.00019

book article
2

book article

Implementation-independent functional test generation for RISC microprocessorsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC 2019 : 27th IFIP/IEEE International Conference on Very Large Scale Integration : [proceedings]2019 / p. 82-87 : ill https://doi.org/10.1109/VLSI-SoC.2019.8920323

book article
3

book article

Implementation-independent test generation for a large class of faults in RISC processor modulesJenihhin, Maksim; Oyeniran, Adeboye Stephen; Raik, Jaan; Ubar, Raimund-Johannes24th Euromicro Conference on Digital System Design (DSD)2021 https://doi.org/10.1109/DSD53832.2021.00090

book article
4

book article EST / book article ENG

On test generation for microprocessors for extended class of functional faultsOyeniran, Adeboye Stephen; Ubar, Raimund-Johannes; Jenihhin, Maksim; Raik, JaanVLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers2020 / p. 21-44 https://doi.org/10.1007/978-3-030-53273-4 Conference proceedings at Scopus Article at Scopus

book article EST / book article ENG

Number of records 4, displaying 1 - 4

1. high-level functional fault model
2. high-level control fault model
3. high-level fault model
4. functional fault model
5. high-level fault coverage
6. high-level fault simulation
7. logic level and high level BDDs
8. low-level fault redundancy
9. fault analysis model
10. stuck-at fault model
11. high level DD (HLDD)
12. high level synthesis
13. high-level control faults
14. high-level decision diagram
15. high-level decision diagrams
16. high-level decision diagrams (HLDD) synthesis
17. high-level expert group on AI
18. High-Level Synthesis (HLS)
19. high-level synthesis for test
20. high-level test data generation
21. high-frequency model
22. High-Pressure High-Temperature Spark Plasma Sintering

match

sort

Otsing
Valikud 0

year of publication

author

TTÜ department

subject term

series

name of the person

keyword

TalTech Library

Akadeemia tee 1

13519

TalTech homepage TalTech Library homepage Digital Collection of TalTech Library Digiteek Repository

6203551

data@taltech.ee

TalTech Raamatukogu