Constraints solving based hierarchical test generation for synchronous sequential circuits = Kitsenduste lahendamisel baseeruv hierarhiline testigenereerimine sünkroonsetele järjestikskeemidele
author
supervisor
statement of authorship
Taavi Viilukas ; [supervisor: Jaan Raik]
type of dissertation
doktoritöö
university/scientific institution
Tallinna Tehnikaülikool
location of publication
Tallinn
publisher
year of publication
pages
150 p. : ill
series
Theses of Tallinn University of Technology. C, Thesis on informatics and system engineering, ISSN 1406-4731 ; 78
subject term
subject of form
ISSN
1406-4731
ISBN
978-9949-23-383-0
978-9949-23-384-7 (pdf)
notes
Includes bibliogr
Thesis (Ph.D. in Computer and System Engineering) : Tallinn University of Technology, 2012
Ka eestikeelse tiitellehega
Autori CV inglise ja eesti keeles, lk. 110-113
Annotatsioon eesti keeles, lk. 9-10
Kättesaadav ka võrguteavikuna
TTÜ department
language
inglise
Viilukas, T. Constraints solving based hierarchical test generation for synchronous sequential circuits = Kitsenduste lahendamisel baseeruv hierarhiline testigenereerimine sünkroonsetele järjestikskeemidele. Tallinn : TUT Press, 2012. 150 p. : ill. (Theses of Tallinn University of Technology. C, Thesis on informatics and system engineering, ISSN 1406-4731 ; 78).