Fast RTL fault simulation using decision diagrams and bitwise set operations
statement of authorship
Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee
source
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada
location of publication
[S.l.]
publisher
year of publication
pages
p. 164-170
conference name, date
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011
conference location
Vancouver, Canada
subject term
ISSN
1550-5774
ISBN
978-1-4577-1713-0
notes
Bibliogr.: 14 ref
language
inglise
Reinsalu, U., Raik, J., Ubar, R., Ellervee, P. Fast RTL fault simulation using decision diagrams and bitwise set operations // 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : 3-5 October 2011, Vancouver, Canada. [S.l.] : IEEE, 2011. p. 164-170.