Hierarchical defect-oriented fault simulation for digital circuits
autor
vastutusandmed
M.Blyzniuk, T.Cibakova, E.Gramatova, W.Kuzmicz, M.Lobur, W.Pleskacz, J.Raik, R.Ubar
allikas
ilmumiskoht
Cascais
ilmumisaasta
leheküljed
p. 151-156
keel
inglise
Blyzniuk, M., Cibakova, T., Gramatova, E., Kuzmicz, W., Lobur, M., Pleskacz, W., Raik, J., Ubar, R. Hierarchical defect-oriented fault simulation for digital circuits // IEEE European Test Workshop. Cascais, 2000. p. 151-156.