Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
autor
Leveugle, R.
Ubar, Raimund-Johannes
vastutusandmed
R. Leveugle, R. Ubar
allikas
Proceedings of the 5th International Conference on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 18-20, 1998
ilmumiskoht
[S.l.]
ilmumisaasta
1998
leheküljed
p. 353-358
keel
inglise