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artikkel ajakirjas

Berechnung von Booleschen Ableitungen bei der Testsatzanalyse für digitale SchaltungenUbar, Raimund-JohannesNachrichtentechnik, Elektronik : technisch-wissenschaftlishe Zeitschrift für die gesamte elektronische Nachrichtentechnik1977 / p. 21-23 : ill https://www.ester.ee/record=b1550811*est

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2

artikkel kogumikus

Boolean fault dignosis with structurally synthesized BDDsUbar, Raimund-JohannesRecent progress in the Boolean domain2014 / p. 303-331 : ill

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3

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Combinatorial calculations in many-dimensional Boolean spaceZakrevskij, Arkadij2012 http://www.ester.ee/record=b2771638*est

raamat

4

artikkel kogumikus

Digital logic simulation with compressed BDDsUbar, Raimund-Johannes; Mironov, Dmitri; Devadze, Sergei; Raik, JaanProceedings : 2011 IEEE International Conference on Computer Science and Automation Engineering : June 10-12, 2011, Shanghai, China2011 / p. 105-109 : ill https://ieeexplore.ieee.org/document/5952643

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Formalization of finite state machines with data path for the verification of high-level synthesisBorrione, Dominique; Dušina, Julia; Pierre, LaurenceXI Brasilian Symposium on Integrated Circuit Design, September 30 - October 3, 1998, Rio de Janeiro, Brazil : proceedings1998 / p. 99-102: ill https://ieeexplore.ieee.org/document/715419

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artikkel kogumikus EST / artikkel kogumikus ENG

From equations to distinctions: Two interpretations of effectful computationsVoorneveld, NielsProceedings of the 8th Workshop on Mathematically Structured Functional Programming, MSFP '20, Dublin, Ireland, 25 April 20202020 / p. 1-17 https://doi.org/10.4204/EPTCS.317.1 Conference Proceedings at Scopus Article at Scopus Article at WOS

artikkel kogumikus EST / artikkel kogumikus ENG

7

artikkel kogumikus

Hardware/software co-design in extensible processing platforms for combinatorial search algorithmsSkliarova, Iouliia; Sklyarov, Valery; Rjabov, Artjom; Sudnitsõn, AleksanderMELECON 2014 : 2014 17th IEEE Mediterranean Electrotechnical Conference : 13-16 April 2014, Beirut, Lebanon2014 / p. 462-466 : ill

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Multiplekserite võrkude süntees Boole'i funktsioonide informatiivse keerukushinnangu aluselTampuu, E.; Keevallik, AndresXXXII üliõpilaste teaduslik-tehnilise konverentsi ettekannete teesid : pühendatud V. I. Lenini 110. sünniaastapäevale : 16.-18. aprill 19801981 / lk. 92 https://www.ester.ee/record=b1322611*est

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artikkel kogumikus

Multiple-objective backtrace for solving test generation constraintsMekler, A.; Raik, JaanInternational Symposium on System-on-Chip : November 19-21, 2003, Tampere, Finland : proceedings2003 / p. 123-126 : ill https://ieeexplore.ieee.org/document/1267732

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On SSBDD model size & complexityJutman, ArturECS'03 : proceedings of the 4th Electronic Circuits and Systems Conference : September 11-12, 2003, Bratislava, Slovakia2003 / p. 17-22 https://pld.ttu.ee/~artur/papers/SSBDD_Model_Size-ECS03.pdf

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Optimization in Boolean spaceZakrevskij, Arkadij; Pottosin, Yu.; Cheremisinova, L.2009 http://www.ester.ee/record=b2461762*est

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artikkel kogumikus EST / artikkel kogumikus ENG

Peirce's sequent proofs of distributivityMa, Minghui; Pietarinen, Ahti-VeikkoLogic and Its Applications : 7th Indian Conference, ICLA 2017, Kanpur, India, January 5-7, 2017 : proceedings2017 / p. 168-182 https://doi.org/10.1007/978-3-662-54069-5_13 Conference proceedings at Scopus Article at Scopus Article at WOS

artikkel kogumikus EST / artikkel kogumikus ENG

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Probabilistic equivalence checking based on high-level decision diagramsKarputkin, Anton; Ubar, Raimund-Johannes; Tombak, Mati; Raik, JaanProceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany2011 / p. 423-428 : ill https://ieeexplore.ieee.org/document/5783130

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Timing simulation of digital circuits with binary decision diagramsUbar, Raimund-Johannes; Jutman, Artur; Peng, Z.Design, Automation and Test in Europe : Conference and Exhibition 2001 : Munich, Germany, March 13-16, 2001 : proceedings2001 / p. 460-466 : ill https://ieeexplore.ieee.org/document/915063

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Using SAT-based techniques in low power state assignmentSagahyroon, Assim; Aloul, Fadi; Sudnitsõn, AleksanderJournal of circuits, systems, and computers2011 / p. 1605-1618 : ill https://www.worldscientific.com/doi/10.1142/S0218126611007980

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Классификация булевых функцииHenno, JaakVII Всесоюзная конференция по математической логике, посвященная 75-летию академика А.И. Мальцева, Новосибирск, 5-7 сент. 1984 г. : Тез. докл.1984 / с. 98-99

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Построение сокращенных дизъюнктивных нормальных форм булевых функций методом масокMihejeva, Ludmilla; Salum, H.Eesti NSV Teaduste Akadeemia toimetised. Füüsika. Matemaatika = Известия Академии наук Эстонской ССР. Физика. Математика = Proceedings of Academy of Sciences of the Estonian SSR. Physics. Mathematics1969 / lk. 458-460 https://www.ester.ee/record=b1264320*est

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