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A new approach to build a low-level malicious fault list starting from high-level description and alternative graphsBenso, A.; Prinetto, Paolo; Rebaudengo, M.; Sonza, M.; Ubar, Raimund-JohannesProceedings IEEE European Design & Test Conference, Paris, March 17-20, 19971997 / p. 560-565 https://ieeexplore.ieee.org/document/582417

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Exploiting high-level descriptions for circuits fault tolerance assessmentsBenso, A.; Prinetto, Paolo; Rebaudengo, M.; Sonza Reorda, Matteo; Raik, Jaan; Ubar, Raimund-Johannes1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 19971997 / p. 212-216 https://ieeexplore.ieee.org/document/628327

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ForewordUbar, Raimund-Johannes; Prinetto, Paolo; Al-Hashimi, BashirInformal Digest of Papers : 10 IEEE European Test Symposium : Tallinn, Estonia, May 22-25, 20052005 / p. III

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10th IEEE European Test SymposiumUbar, Raimund-Johannes; Prinetto, Paolo; Raik, JaanIEEE journal of design & test of computers2005 / p. 480-481 : phot http://dx.doi.org/10.1109/MDT.2005.106

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Prinetto, Paolo (autor)

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autor 17