prindi

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation

autor
Leveugle, R.
Ubar, Raimund-Johannes
vastutusandmed
R.Leveugle, R.Ubar
allikas
Electron technology
ajakirja aastakäik number kuu
Vol. 32
ilmumisaasta
1999
leheküljed
3, p. 282-287 : ill
konverentsi nimetus, aeg
5th International Conference MIXDES'98 "Mixed design of integrated circuits and systems", June 18-20, 1998
konverentsi toimumispaik
Lodz, Poland
märksõna
otsustusdiagrammid
süntees
VHDL (programmeerimiskeel)
märkused
Ajakiri sisaldab konverentsi "5th International Conference MIXDES'98 "Mixed design of integrated circuits and systems", Lodz, Poland, June 18-20, 1998" materjale
keel
inglise
Leveugle, R., Ubar, R. Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation // Electron technology (1999) Vol. 32, 3, p. 282-287 : ill.