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26
book article
Fast fault emulation for synchronous sequential circuits
Raik, Jaan
;
Ellervee, Peeter
;
Tihhomirov, Valentin
;
Ubar, Raimund-Johannes
Proceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 2004
2004
/
p. 35-40
https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=a6eb712498a5f23db3f95ad66bada257c21e96f0
book article
27
book article
Fast fault simulation for extended class of faults in scan-path circuits
Ubar, Raimund-Johannes
;
Devadze, Sergei
;
Raik, Jaan
;
Jutman, Artur
Proceedings : Fifth IEEE International Symposium on Electronic Design, Test and Applications : DELTA 2010 : 13-15 January 2010, Ho Chi Minh City, Vietnam
2010
/
p. 14-19
https://ieeexplore.ieee.org/document/5438717
book article
28
book article
Fault collapsing in digital circuits using fast fault dominance and equivalence analysis with SSBDDs
Ubar, Raimund-Johannes
;
Jürimägi, Lembit
;
Orasson, Elmet
;
Raik, Jaan
VLSI-SoC : Design for Reliability, Security, and Low Power : 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 Daejeon, Korea, October 5-7, 2015 : revised selected papers
2016
/
p. 23-45 : ill
http://dx.doi.org/10.1007/978-3-319-46097-0_2
book article
29
dissertation
Fault simulation of digital systems = Digitaalsüsteemide rikete simuleerimine
Devadze, Sergei
2009
https://digi.lib.ttu.ee/i/?445
https://www.ester.ee/record=b2508727*est
dissertation
30
book article
FPGA implementation of the polynomial curve fitting
Gorev, Maksim
;
Pesonen, Vadim
Info- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve
2011
/
p. 121-124 : ill
book article
31
journal article
FPGA-based fault emulation of synchronous sequential circuits
Ellervee, Peeter
;
Raik, Jaan
;
Tammemäe, Kalle
;
Ubar, Raimund-Johannes
IET computers and digital techniques
2007
/
2, p. 70-76 : ill
https://ieeexplore.ieee.org/abstract/document/1423822
journal article
32
book article
FPGA-based implementation of EEG analyzer
Gorev, Maksim
;
Pesonen, Vadim
;
Mihhailov, Dmitri
;
Jenihhin, Maksim
;
Ellervee, Peeter
DATE'11 Friday Workshop on "Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing" : Grenoble, France, March 2011
2011
/
[1] p
https://www.microsoft.com/en-us/research/wp-content/uploads/2017/03/ellervee.pdf
book article
33
book article
FPGA-based systems in information and communication
Sklyarov, Valery
;
Skliarova, Iouliia
;
Sudnitsõn, Aleksander
AICT2011 : 5th International Conference on Application of Information and Communication Technologies : 12-14 October, Baku, Azerbaijan : conference proceedings
2011
/
p. 551-555
https://www.researchgate.net/publication/254014990_FPGA-based_systems_in_information_and_communication
book article
34
book article
Functional level controllability analysis for digital circuits
Ubar, Raimund-Johannes
;
Kuchcinski, Ktzysztof
Proc. of the Design Automation Conference, Kaunas, Lithuania, June 1-4, 1992
1992
/
p. 13-21
book article
35
journal article
Functional self-test of high-performance pipe-lined signal processing architectures
Gorev, Maksim
;
Ubar, Raimund-Johannes
;
Ellervee, Peeter
;
Devadze, Sergei
;
Raik, Jaan
;
Min, Mart
Microprocessors and microsystems
2015
/
p. 909-918 : ill
http://dx.doi.org/10.1016/j.micpro.2014.11.002
journal article
36
dissertation
Hierarchical test generation for digital circuits represented by Decision Diagrams : thesis on informatics and system engineering
Raik, Jaan
2001
https://www.ester.ee/record=b1578107*est
dissertation
37
dissertation
Hierarchical test pattern generation and untestability identification techniques for synchronous sequential circuits = Hierarhilised testintegreerimise ja mittetestitavuse identifitseerimise meetodid sünkroonsetele järjestikskeemidele
Rannaste, Anna
2010
https://www.ester.ee/record=b2637391*est
dissertation
38
journal article
Hierarhilisest testigenereerimisest ja mittetestitavuse analüüsist
Rannaste, Anna
A & A
2010
/
4, lk. 38-39
https://artiklid.elnet.ee/record=b2286481*est
journal article
39
dissertation
Hybrid built-in self-test : methods and tools for analysis and optimization of BIST = Sisseehitatud hübriidne isetestimine : meetodid ja vahendid analüüsiks ning optimeerimiseks
Orasson, Elmet
2007
https://www.ester.ee/record=b2305436*est
dissertation
40
book article
Improved fault emulation for synchronous sequential circuits
Raik, Jaan
;
Ellervee, Peeter
;
Tihhomirov, Valentin
;
Ubar, Raimund-Johannes
Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 2005
2005
/
p. 72-78 : ill
book article
41
book article
Improved testability calculation for digital circuits
Ubar, Raimund-Johannes
;
Heinlaid, J.
;
Raun, L.
19th NORCHIP Conference, Kista, Sweden, 12-13 November 2001 : proceedings
2001
/
p. 264-270 : ill
book article
42
dissertation
Investigation and development of test generation methods for control part of digital systems
Brik, Marina
2002
http://www.ester.ee/record=b1688656*est
dissertation
43
book article
LFSR polynomial and seed selection using genetic algorithm
Aleksejev, E.
;
Jutman, Artur
;
Ubar, Raimund-Johannes
BEC 2006 : 2006 International Baltic Electronics Conference : Tallinn University of Technology, October 2-4, 2006, Tallinn, Estonia : proceedings of the 10th Biennial Baltic Electronics Conference
2006
/
p. 179-182 : ill
book article
44
book article
Logic simulation and fault collapsing with shared structurally synthesized BDDs
Mironov, Dmitri
;
Ubar, Raimund-Johannes
;
Raik, Jaan
2014 19th IEEE European Test Symposium (ETS) : May 26th-30th, 2014, Paderborn, Germany : proceedings
2014
/
[2] p. : ill
book article
45
book article
Lower bounds of the size of shared structurally synthesized BDDs
Ubar, Raimund-Johannes
;
Mironov, Dmitri
Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) : April 23-25, 2014, Warsaw, Poland
2014
/
p. 77-82 : ill
book article
46
book article
Macro level defect-oriented diagnosability of digital circuits
Kostin, Sergei
;
Ubar, Raimund-Johannes
;
Raik, Jaan
Info- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis
2010
/
lk. 53-56 : ill
book article
47
book article
Macro level defect-oriented diagnosability of digital circuits
Kostin, Sergei
;
Ubar, Raimund-Johannes
;
Raik, Jaan
BEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia
2010
/
p. 149-152 : ill
book article
48
book article
Mixed-level defect simulation in data-paths of digital systems
Ubar, Raimund-Johannes
;
Raik, Jaan
;
Ivask, Eero
;
Brik, Marina
23rd International Conference on Microelectronics : MIEL 2002, Niš, Yugoslavia, 12-15 May 2002 : proceedings. Volume 2
2002
/
p. 617-620 : ill
https://ieeexplore.ieee.org/document/1003333
book article
49
book article
Modeling sequential circuits with shared structurally synthesized BDDs
Ubar, Raimund-Johannes
;
Marenkov, Mihhail
;
Mironov, Dmitri
;
Viies, Vladimir
Proceedings of 2014 9th International Design & Test Symposium (IDT) : Sheraton Club des Pins Hotel, Algiers, Algeria, December 16-18, 2014
2014
/
p. 130-135 : ill
book article
50
book article
Multi-level test generation and fault diagnosis for finite state machines
Ubar, Raimund-Johannes
;
Brik, Marina
Dependable computing : proceedings / EDCC-2, Second European Dependable Computing Conference, Taormina, Italy, October 2-4, 1996
1996
/
p. 264-281: ill
book article
Number of records 79, displaying
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