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book article

Evalutionary two-criteria optimization of finite state machinesSpitšakova, MargaritaInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK neljanda aastakonverentsi artiklite kogumik : 26.-27. novembril 2010, Essu mõis2010 / lk. 101-104

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27

book article

Evolutionary approach to the functional test generation for digital circuitsSkobtsov, Y.A.; Ivanov, D.E.; Skobtsov, V.Y.; Ubar, Raimund-JohannesBEC 2004 : proceedings of the 9th Biennial Baltic Electronics Conference : October 3-6, 2004, Tallinn, Estonia2004 / p. 229-232 : ill

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28

book article

Fast fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings of East–West Design & Test Workshop (EWDTW’04) : Yalta, Alushta, Crimea, Ukraine, September 23-26, 20042004 / p. 35-40 https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=a6eb712498a5f23db3f95ad66bada257c21e96f0

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29

book article

Fast fault simulation for extended class of faults in scan-path circuitsUbar, Raimund-Johannes; Devadze, Sergei; Raik, Jaan; Jutman, ArturProceedings : Fifth IEEE International Symposium on Electronic Design, Test and Applications : DELTA 2010 : 13-15 January 2010, Ho Chi Minh City, Vietnam2010 / p. 14-19 https://ieeexplore.ieee.org/document/5438717

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30

book article EST / book article ENG

Fault collapsing in digital circuits using fast fault dominance and equivalence analysis with SSBDDsUbar, Raimund-Johannes; Jürimägi, Lembit; Orasson, Elmet; Raik, JaanVLSI-SoC : Design for Reliability, Security, and Low Power : 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015 Daejeon, Korea, October 5-7, 2015 : revised selected papers2016 / p. 23-45 : ill https://doi.org/10.1007/978-3-319-46097-0_2 Conference Proceedings at Scopus Article at Scopus Article at WOS

book article EST / book article ENG

31

dissertation

Fault simulation of digital systems = Digitaalsüsteemide rikete simuleerimineDevadze, Sergei2009 https://digi.lib.ttu.ee/i/?445 https://www.ester.ee/record=b2508727*est

dissertation

32

book article

Finite state machine synthesis for low power using input-disabling precomputation architecturesSudnitsõn, AleksanderThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 137-140 : ill

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33

book article

FPGA implementation of the polynomial curve fittingGorev, Maksim; Pesonen, VadimInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK viienda aastakonverentsi artiklite kogumik : 25.-26. novembril 2011, Nelijärve2011 / p. 121-124 : ill

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34

journal article

FPGA-based fault emulation of synchronous sequential circuitsEllervee, Peeter; Raik, Jaan; Tammemäe, Kalle; Ubar, Raimund-JohannesIET computers and digital techniques2007 / 2, p. 70-76 : ill https://ieeexplore.ieee.org/abstract/document/1423822

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35

book article

FPGA-based implementation of EEG analyzerGorev, Maksim; Pesonen, Vadim; Mihhailov, Dmitri; Jenihhin, Maksim; Ellervee, PeeterDATE'11 Friday Workshop on "Design Methods and Tools for FPGA-Based Acceleration of Scientific Computing" : Grenoble, France, March 20112011 / [1] p https://www.microsoft.com/en-us/research/wp-content/uploads/2017/03/ellervee.pdf

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36

book article

FPGA-based systems in information and communicationSklyarov, Valery; Skliarova, Iouliia; Sudnitsõn, AleksanderAICT2011 : 5th International Conference on Application of Information and Communication Technologies : 12-14 October, Baku, Azerbaijan : conference proceedings2011 / p. 551-555 https://www.researchgate.net/publication/254014990_FPGA-based_systems_in_information_and_communication

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37

book article

Functional level controllability analysis for digital circuitsUbar, Raimund-Johannes; Kuchcinski, KtzysztofProc. of the Design Automation Conference, Kaunas, Lithuania, June 1-4, 19921992 / p. 13-21

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38

book

Functional level testability analysis for digital circuitsUbar, Raimund-Johannes1992

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39

journal article EST / journal article ENG

Functional self-test of high-performance pipe-lined signal processing architecturesGorev, Maksim; Ubar, Raimund-Johannes; Ellervee, Peeter; Devadze, Sergei; Raik, Jaan; Min, MartMicroprocessors and microsystems2015 / p. 909-918 : ill https://doi.org/10.1016/j.micpro.2014.11.002 Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

40

book article

Hierarchical defect-oriented fault simulation for digital circuitsBlyzniuk, M.; Cibakova, Tatiana; Gramatova, Elena; Kuzmicz, W.; Lobur, M.; Pleskacz, Witold A.; Raik, Jaan; Ubar, Raimund-JohannesIEEE European Test Workshop : 23-26 May 2000, Cascais, Portugal : ETW 2000 : proceedings2000 / p. 69-74 : ill https://ieeexplore.ieee.org/document/873781

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41

book article

Hierarchical fault simulation for finite state machinesBrik, Marina; Raik, Jaan; Ubar, Raimund-JohannesThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 145-148 : ill

book article

42

dissertation

Hierarchical test generation for digital circuits represented by Decision Diagrams : thesis on informatics and system engineeringRaik, Jaan2001 https://www.ester.ee/record=b1578107*est

dissertation

43

dissertation

Hierarchical test pattern generation and untestability identification techniques for synchronous sequential circuits = Hierarhilised testintegreerimise ja mittetestitavuse identifitseerimise meetodid sünkroonsetele järjestikskeemideleRannaste, Anna2010 https://www.ester.ee/record=b2637391*est

dissertation

44

journal article

Hierarhilisest testigenereerimisest ja mittetestitavuse analüüsistRannaste, AnnaA & A2010 / 4, lk. 38-39 https://artiklid.elnet.ee/record=b2286481*est

journal article

45

book article

High-level decision diagrams based coverage metrics for verification and testJenihhin, Maksim; Raik, Jaan; Tšepurov, Anton; Reinsalu, Uljana; Ubar, Raimund-JohannesLATW 2009 : 10th IEEE Latin American Test Workshop : Buzios, Rio de Janero, Brazil, March 2-5, 20092009 / [6] p. : ill http://dx.doi.org/10.1109/LATW.2009.4813792

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46

dissertation

Hybrid built-in self-test : methods and tools for analysis and optimization of BIST = Sisseehitatud hübriidne isetestimine : meetodid ja vahendid analüüsiks ning optimeerimiseksOrasson, Elmet2007 https://www.ester.ee/record=b2305436*est

dissertation

47

book article

Improved fault emulation for synchronous sequential circuitsRaik, Jaan; Ellervee, Peeter; Tihhomirov, Valentin; Ubar, Raimund-JohannesProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 72-78 : ill

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48

book article

Improved testability calculation for digital circuitsUbar, Raimund-Johannes; Heinlaid, J.; Raun, L.19th NORCHIP Conference, Kista, Sweden, 12-13 November 2001 : proceedings2001 / p. 264-270 : ill

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49

book article

Increasing the speed of delay simulation in digital circuitsUbar, Raimund-Johannes; Jutman, ArturThe 7th Biennial Conference on Electronics and Microsystem Technology "Baltic Electronics Conference" : BEC 2000 : October 8 - 11, 2000, Tallinn, Estonia : conference proceedings2000 / p. 31-34 : ill

book article

50

dissertation

Investigation and development of test generation methods for control part of digital systemsBrik, Marina2002 http://www.ester.ee/record=b1688656*est

dissertation

digitaalintegraallülitused (subject term)

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