Comprehensive performance and robustness analysis of 2D turn models for network-on-chips

vastutusandmed
Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Thilo Kogge, Jaan Raik, Gert Jervan, Thomas Hollstein
allikas
2017 IEEE International Symposium on Circuits and Systems (ISCAS)
ilmumiskoht
Piscataway
kirjastus/väljaandja
ilmumisaasta
leheküljed
p. 1476-1479 : ill
konverentsi nimetus, aeg
50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, 28.-31. May, 2017
konverentsi toimumispaik
Baltimore, United States
võtmesõna
turn model
robustness
minimal path
ISSN
2379-447X
ISBN
978-1-4673-6852-0
märkused
bibliogr.: 13 ref
TTÜ struktuuriüksus
keel
inglise
Azad, S.P., Niazmand, B., Janson, K., Raik, J., Jervan, G., Hollstein, T. et al. Comprehensive performance and robustness analysis of 2D turn models for network-on-chips // 2017 IEEE International Symposium on Circuits and Systems (ISCAS). Piscataway : IEEE, 2017. p. 1476-1479 : ill.