Centre for hardware security
TalTech priority area
Research classification (Frascati)
Head of the research group
Research group member
Doctoral students
Keyword
hardware security
trustworthy integrated circuits
ASICs
crypto hardware
obfuscation
Overview
The Centre for Hardware Security conductsresearch in all applied aspects of hardwaresecurity: the aim is to validate security techniques in real silicon. The Centre’s research onintegrated circuit (IC) design, electronic designautomation (EDA), and cryptographic hardwareenables trustworthy IC-based systems to bebuilt. Threats such as hardware Trojans, reverseengineering, circuit (de)obfuscation, IP piracy,IC overbuilding, side-channel attacks, etc., areaddressed through an array of technical countermeasures. Core competences of the centre are: Design of Application Specific IntegratedCircuits. Circuit obfuscation by design partitioningand locking. Trustworthy electronic design automationtooling (from RTL to layout). Countermeasures to reverse engineering,side channel attacks, and piracy. Crypto hardware, including conventionaland post-quantum cryptography.
Related projects
Related department
Publications related to the research group
- Perez, T., Pagliarini, S. Hardware trojan insertion in finalized layouts : from methodology to a silicon demonstration // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2023) vol. 42, 7, p. 2094-2107.
https://doi.org/10.1109/TCAD.2022.3223846 - Aikata, A., Mert, A. C., Imran, M., Pagliarini, S., Roy, S. S. KaLi: a crystal for post-quantum security using kyber and dilithium // IEEE Transactions on Circuits and Systems I : regular papers (2023) vol. 70, 2, p. 747–758.
https://doi.org/10.1109/TCSI.2022.3219555 - Aksoy, L., Roy, D. B., Imran, M., Karl, P., Pagliarini, S. Multiplierless design of very large constant multiplications in cryptography // IEEE Transactions on Circuits and Systems II : Express Briefs (2022) vol. 69, 11, p. 4503-4507.
https://doi.org/10.1109/TCSII.2022.3191662 - Pagliarini, S., Benites, L., Martins, M., Rech, P., Kastensmidt, F. Evaluating architectural, redundancy, and implementation strategies for radiation hardening of FinFET integrated circuits // IEEE transactions on nuclear science (2021) vol. 68, 5, p. 1045-1053.
https://doi.org/10.1109/TNS.2021.3070643 - Imran, M., Abideen, Z.U., Pagliarini, S. An open-source library of large integer polynomial multipliers // 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, Austria, April 7-9 2021. : IEEE, 2021. p. 145-150 : ill.
https://doi.org/10.1109/DDECS52668.2021.9417065 - Perez, T.D., Pagliarini, S.N. A survey on split manufacturing : attacks, defenses, and challenges // IEEE Access (2020) vol. 8, p. 184013-184035.
https://doi.org/10.1109/ACCESS.2020.3029339 - Sweeney, J., Mohammed Zackriya, V., Pagliarini, S., Pileggi, L. Latch-Based logic locking // Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2020. Danvers : IEEE, 2020. p. 132−141 : ill.
https://doi.org/10.1109/HOST45689.2020.9300256 - Imran, M., Pagliarini, S., Rashid, M. An area aware accelerator for elliptic curve point multiplication // 27th IEEE International Conference on Electronics Circuits and Systems, (ICECS) 2020, Glasgow, UK, Virtual Conference, November 23-25, 2020 : proceedings. Danvers : IEEE, 2020. 4 p.
https://doi.org/10.1109/ICECS49266.2020.9294908 - Hafeez, M.A., Rashid, M., Tariq, H., Abideen, Z.U., Alotaibi, S.S., Sinky, M.H. Performance improvement of decision tree : a robust classifier using tabu search algorithm // Applied Sciences (Switzerland) (2021) Vol. 11, 15, art. 6728.
https://doi.org/10.3390/app11156728 - Rashid, M., Imran, M., Jafri, A. R., Mehmood, Z. A 4-Stage pipelined architecture for point multiplication of binary huff curves // Journal of circuits, systems, and computers (2020) vol. 29, 11, art. 2050179.
https://doi.org/10.1142/S0218126620501790 - Imran, M., Abideen, Z.U., Pagliarini, S. An experimental study of building blocks of lattice-based NIST post-quantum cryptographic algorithms // Electronics (2020) vol. 9, 11, art. 1953, 26 p. : ill.
https://doi.org/10.3390/electronics9111953 - Perez, T.D., Imran, M., Vaz, P., Pagliarini, S.N. Side-channel Trojan insertion - a practical foundry-side attack via ECO // 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, May 22-28, 2021 : proceedings. Danvers : IEEE, 2021. 5 p. : ill.
https://doi.org/10.1109/ISCAS51556.2021.9401481 - Abideen, Z. U., Perez, T. D., Pagliarini, S. From FPGAs to obfuscated eASICs : design and security trade-offs // IEEE Asian Hardware-Oriented Security and Trust (AsianHOST). : IEEE, 2021. p. 1-4.
https://doi.org/10.1109/AsianHOST53231.2021.9699758 - Hepp, A., Perez, T., Pagliarini, S., Sigl, G. A pragmatic methodology for blind hardware trojan insertion in finalized layouts // ICCAD '22: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design. New York : IEEE, 2022. art. 69, p. 1-9 : ill.
https://doi.org/10.1145/3508352.3549452 - Aksoy, L., Nguyen, Q.-L., Almeida, F., Raik, J., Flottes, M.-L., Dupuis, S., Pagliarini, S. High-level intellectual property obfuscation via decoy constants // 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS) : Torino, Italy, 28-30 June 2021. : IEEE, 2021. p. 1-7.
https://doi.org/10.1109/IOLTS52814.2021.9486714 - Abideen, Z.U., Rashid, M. EFIC-ME : a fast emulation based fault injection control and monitoring enhancement // IEEE Access (2020) vol. 8, p. 207705-207716.
https://doi.org/10.1109/ACCESS.2020.3038198 - Sajid, A., Rashid, M., Jamal, S.S., Imran, M., Alotaibi, S.S., Sinky, M.H. Areeba : an area efficient binary huff-curve architecture // Electronics (Switzerland) (2021) Vol. 10, 12, art. 1490.
https://doi.org/10.3390/electronics10121490 - Almeida, F., Imran, M., Raik, J., Pagliarini, S. Ransomware attack as Hardware Trojan : a feasibility and demonstration study // IEEE Access (2022) vol. 10, p. 44827-44839.
https://doi.org/10.1109/ACCESS.2022.3168991 - Aljafar, M. J., Acken, J. M. A 3-D crossbar architecture for both pipeline and parallel computations // IEEE Transactions on Circuits and Systems I : regular papers (2021) vol. 68, 11, p. 4456-4469.
https://doi.org/10.1109/TCSI.2021.3108564 https://pdxscholar.library.pdx.edu/cgi/viewcontent.cgi?article=1680&context=ece_fac - Pagliarini, S., Sweeney, J., Mai, K. et al. Split-chip design to prevent IP reverse engineering // IEEE Design and Test (2020) vol. 38, 4, p. 109-118.
https://doi.org/10.1109/MDAT.2020.3033255 - Aljafar, M. J., Acken, J. M. Survey on the benefits of using memristors for PUFs // International Journal of Parallel, Emergent and Distributed Systems (2022) vol. 37, 1, p. 40-67.
https://doi.org/10.1080/17445760.2021.1972295 - Basiashvili, G., Abideen, Z.U., Pagliarini, S. Obfuscating the hierarchy of a digital IP // Embedded Computer Systems : Architectures, Modeling, and Simulation :22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022 : proceedings. Cham : Springer, 2022. p. 303-314. (Lecture notes in computer science ; 13511).
https://doi.org/10.1007/978-3-031-15074-6_28 - Di Natale, G., Regazzoni, F., Albanese, V., Pagliarini, S. et al. Latest trends in hardware security and privacy // 33rd IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) : ESA-ESRIN, Italy (On-line Virtual Event),October 19–21, 2020. : IEEE, 2020. 4 p. : ill.
https://doi.org/10.1109/DFT50435.2020.9250816 - Perez, T., Pagliarini, S. A side-channel hardware trojan in 65nm CMOS with 2μW precision and multi-bit leakage capability // 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) : 17-20 January 2022 : Taipei, Taiwan. : IEEE, 2022. p. 9-10 : ill.
https://doi.org/10.1109/ASP-DAC52403.2022.9712490 - Eslami, M., Ghasempouri, T., Pagliarini, S. Reusing verification assertions as security checkers for Hardware Trojan detection // 2022 23rd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA : 06-07 April 2022. : IEEE, 2022. p. 1-6 : ill.
https://doi.org/10.1109/ISQED54688.2022.9806292 - Aksoy, L., Hepp, A., Baehr, J., Pagliarini, S. Hardware obfuscation of digital FIR filters // 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) : Prague, Czech Republic : April 6-8, 2022 : proceedings. : IEEE, 2022. p. 68-73.
https://doi.org/10.48550/arXiv.2202.10022 https://doi.org/10.1109/DDECS54261.2022.9770141 - Almeida, F., Aksoy, L., Raik, J., Pagliarini, S. Side-channel attacks on triple modular redundancy schemes // 2021 IEEE 30th Asian Test Symposium ATS 2021 : proceedings. : IEEE, 2021. p. 79-84 : ill.
https://doi.org/10.1109/ATS52891.2021.00026 - Grailoo, M., Leier, M., Pagliarini, S. Hardware Trojans for confidence reduction and misclassifications on neural networks // Proceedings Of The Twenty Third International Symposium On Quality Electronic Design (ISQED 2022). Danvers : IEEE, 2022. art. 180541, p. 230-235. (International Symposium on Quality Electronic Design).
https://doi.org/10.1109/ISQED54688.2022.9806246 - Perez, T.D., Gonçalves, M.M., Gobatto, L., Brandalero, M., Azambuja, J.R., Pagliarini, S. G-GPU : a fully-automated generator of GPU-like ASIC accelerators // 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) : 14-23 March 2022 : Antwerp, Belgium. : IEEE, 2022. p. 544 - 547.
https://doi.org/10.23919/DATE54114.2022.9774758 - Aljafar, M.J., Azaïs, F., Flottes, M-L., Pagliarini, S. Leveraging layout-based effects for locking analog ICs // ASHES'22: Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security. New York : ACM, 2022. p. 5-13.
https://doi.org/10.1145/3560834.3563826 - Pagliarini, S. A tutorial on design obfuscation : from transistors to systems // 2021 IEEE 22nd Latin American Test Symposium (LATS), Punta del Este, Uruguay, 27-29 October 2021. : IEEE, 2021. 3 p. : ill.
https://doi.org/10.1109/LATS53581.2021.9651741 - Farahmandi, F., Sinanoglu, O., Blanton, R., Pagliarini, S. Design obfuscation versus test // 2020 IEEE European Test Symposium (ETS) : ETS 2020, May 25 - 29, 2020, Tallinn, Estonia. Danvers : IEEE, 2020. 10 p.
https://doi.org/10.1109/ETS48528.2020.9131590 - Pagliarini, S.N., Bhuin, S., Isgenc, M.M., Biswas, A.K., Pileggi, L. A probabilistic synapse with strained MTJs for Spiking Neural Networks // IEEE Transactions on Neural Networks and Learning Systems (2020) vol. 31, no. 4, p. 1113-1123 : ill.
https://doi.org/10.1109/TNNLS.2019.2917819 - Rashid, M., Jamal, S.S., Khan, S.Z., Alharbi, A.R., Aljaedi, A., Imran, M. Elliptic-curve crypto processor for RFID applications // Applied Sciences (Switzerland) (2021) Vol. 11, 15, art. 7079.
https://doi.org/10.3390/app11157079 - Imran, M., Almeida, F., Basso, A., Sinha Roy, S., Pagliarini, S. High-speed SABER key encapsulation mechanism in 65nm CMOS // Journal of cryptographic engineering (2023) vol. 13, p. 461-471 : ill.
https://doi.org/10.1007/s13389-023-00316-2 - Abideen, Z.U., Perez, T.D., Martins, M., Pagliarini, S.N. A security-aware and LUT-based CAD flow for the physical synthesis of hASICs // IEEE transactions on computer-aided design of integrated circuits and systems (2023) vol. 42, 10, p. 3157-3170 : ill.
https://doi.org/10.1109/TCAD.2023.3244879 - Abideen, Z.U., Tariq, H., Hafeez, M.A., Subhani, Z.M. An improved implementation of shift displacement method on hardware —comprehensive evaluation of emerging bi-pedal techniques // 2020 4th International Conference on Automation, Control and Robots : Rome, Italy, 11-13 October 2020. : IEEE, 2020. p. 7-12 : ill.
https://doi.org/10.1109/ICACR51161.2020.9265496 - Martins, M.G.A., Pagliarini, S.N., Isgenc, M.M., Pileggi, L. From virtual characterization to test-chips : DFM analysis through pattern enumeration // IEEE transactions on computer-aided design of integrated circuits and systems (2020) vol. 39, no. 2, p. 520-532.
https://doi.org//10.1109/TCAD.2018.2889772 - Isgenc, M.M., Martins, M.G.A., Zackriya, M., Pagliarini, S.N., Pileggi, L. Logic IP for low-cost IC design in advanced CMOS nodes // IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2020) vol. 28, no. 2, p. 585-595.
https://doi.org//10.1109/TVLSI.2019.2942825 - Eslami, M., Knechtel, J., Sinanoglu, O., Karri, R., Pagliarini, S. Benchmarking advanced security closure of physical layouts // ISPD '23 : proceedings of the 2023 International Symposium on Physical Design. New York : ACM, 2023. p. 256-264.
https://doi.org/10.1145/3569052.3578924 https://dl.acm.org/doi/pdf/10.1145/3569052.3578924 - Almeida, F., Aksoy, L., Nguyen, Q-L., Dupuis, S., Flottes, M.-L., Pagliarini, S. N. Resynthesis-based attacks against logic locking // 2023 24th International Symposium on Quality Electronic Design (ISQED) : San Francisco, 5-7 April 2023. San Francisco, California : IEEE, 2023. 8 p. : ill.
https://doi.org/10.1109/ISQED57927.2023.10129403 - Aksoy, L., Nguyen, Q.-L., Almeida, F., Raik, J., Flottes, M.-L., Dupuis, S., Pagliarini, S. Hybrid protection of digital FIR filters // IEEE transactions on Very Large Scale Integration (VLSI) Systems (2023) Vol. 31, 6, p. 812-825 : ill.
https://doi.org/10.1109/TVLSI.2023.3253641