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New fault models and self-test generation for microprocessors using High-Level Decision Diagrams (title)
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book article
New fault models and self-test generation for microprocessors using High-Level Decision Diagrams
Jasnetski, Artjom
;
Raik, Jaan
;
Tšertov, Anton
;
Ubar, Raimund-Johannes
2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings
2015
/
p. 251-254 : ill
book article
Number of records 1, displaying
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keyword
15
1.
high-level decision diagrams
2.
high-level decision diagrams (HLDD) synthesis
3.
High-level Decision Diagrams for Modeling Digital Systems
4.
high-level test data generation
5.
test generation and fault diagnosis
6.
behaviour level test generation
7.
Hierarchical Multi-level Test Generation
8.
high-level control fault model
9.
high-level decision diagram
10.
high-level fault coverage
11.
high-level fault model
12.
high-level fault simulation
13.
high-level functional fault model
14.
high-level synthesis for test
15.
logic level and high level BDDs
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