New fault models and self-test generation for microprocessors using High-Level Decision Diagrams
statement of authorship
Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
location of publication
Los Alamitos
publisher
year of publication
pages
p. 251-254 : ill
conference name, date
18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015, 22-24 April, 2015
conference location
Belgrade, Serbia
ISBN
978-1-4799-6780-3
notes
Bibliogr.: 22 ref
TTÜ department
language
inglise
Jasnetski, A., Raik, J., Tšertov, A., Ubar, R. New fault models and self-test generation for microprocessors using High-Level Decision Diagrams // 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems DDECS 2015 : 22-24 April 2015, Belgrade, Serbia : proceedings. Los Alamitos : IEEE Computer Society, 2015. p. 251-254 : ill.