Searching - TalTech Research Portal

display

sort

76

newspaper article

Gert Jervan: Tehisintellektiga on praegu nii nagu kunagi tuumarelvadega – tõestada, et me suudame seda tehaTammepuu, Kadri; Jervan, Gerttv.postimees.ee2023 Gert Jervan: Tehisintellektiga on praegu nii nagu kunagi tuumarelvadega – tõestada, et me suudame seda teha

newspaper article

77

book article

Graduate School in Information and Communication Technologies : experiences at Tallinn University of TechnologyJervan, Gert; Kruus, Margus; Rüstern, EnnuProceedings MSE 2007 : 2007 IEEE International Conference on Microelectronic Systems Education : 3-4 June 2007, San Diego, CA2007 / p. 25-26

book article

78

book article

Handling of SETs on NoC links by exploitation of inherent redundancy in circular input buffers [Online resource]Janson, Karl; Pihlak, Rene; Azad, Siavoosh Payandeh; Niazmand, Behrad; Jervan, Gert; Raik, JaanBEC 2018 : 2018 16th Biennial Baltic Electronics Conference (BEC) : proceedings of the 16th Biennial Baltic Electronics Conference, October 8-10, 20182018 / 4 p.: ill https://doi.org/10.1109/BEC.2018.8600989

book article

79

journal article

Head lõpetajad! = Dear graduates!Land, Tiit; Sergejev, Fjodor; Jervan, Gert; Salupere, Andrus; Listra, Enn; Leiger, RoometMente et Manu2021 / lk. 30-50 : fot https://www.ester.ee/record=b1242496*est

journal article

80

book article

A hierarchical approach for devising area efficient concurrent online checkersNiazmand, Behrad; Azad, Siavoosh Payandeh; Ghasempouri, Tara; Raik, Jaan; Jervan, GertProceedings 2nd IEEE International Test Conference in Asia : ITC-Asia 2018, 15-17 August 2018, Harbin, China2018 / p. 139-144 : ill https://doi.org/10.1109/ITC-Asia.2018.00034

book article

81

book article

A hierarchical automatic test pattern generator based on using alternative graphsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 4th International Workshop Mixed Design of Integrated Circuits and Systems : MIXDES'97 : Poznan, Poland, 12-14 June 19971997 / p. 415-420

book article

82

book article

Hierarchical calculation of malicious faults for evaluating the fault-toleranceUbar, Raimund-Johannes; Devadze, Sergei; Jenihhin, Maksim; Raik, Jaan; Jervan, Gert; Ellervee, PeeterProceedings : Fourth IEEE International Symposium on Electronic Design, Test and Applications : [DELTA 2008] : 23-25 January 2008, Hong Kong, SAR, China2008 / p. 222-227 : ill https://ieeexplore.ieee.org/document/4459544

book article

83

book article

Hierarchical test generation for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesMixed design of integrated circuits and systems1998 / p. 131-136: ill

book article

84

book article

Hierarchical test generation with multi-level decision diagram modelsJervan, Gert; Markus, Antti; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the 7th IEEE North Atlantic Test Workshop, West Greenwich RI, USA, May 28-29, 19981998 / p. 26-33

book article

85

book article

High-level synthesis and test in the MOSCITO-based virtual laboratorySchneider, Andre; Diener, Karl-Heinz; Jervan, Gert; Peng, Z.; Raik, Jaan; Ubar, Raimund-Johannes; Hollstein, Thomas; Glesner, M.BEC 2002 : proceedings of the 8th Biennial Baltic Electronics Conference : October 6-9, 2002, Tallinn, Estonia2002 / p. 287-290 : ill

book article

86

book article

High-level test synthesis with hierarchical test generationJervan, Gert; Eles, Petru; Peng, Zebo; Raik, Jaan; Ubar, Raimund-Johannes17th NORCHIP Conference : Oslo, Norway, 8-9 November 1999 : proceedings1999 / p. 291-296

book article

87

newspaper article

Hirm masinate ees: tehisintellekti liiga kiirele arengule tõmmatakse piduritStrandberg, Marek; Einama, KaidoPostimees2023 / lk. 5 https://dea.digar.ee/article/postimees/2023/03/31/3.11 Hirm masinate ees: tehisintellekti liiga kiirele arengule tahetakse tõmmata pidurit

newspaper article

88

journal article

Holistic approach for Fault-Tolerant Network-on-Chip based many-core systems [Online resource]Azad, Siavoosh Payandeh; Niazmand, Behrad; Raik, Jaan; Jervan, Gert; Hollstein, ThomasarXiv.org2016 / [8] p. : ill

journal article

89

book article

How to emulate Network-on-Chip?Ellervee, Peeter; Jervan, GertProceedings of the IEEE East-West Design & Test Workshop (EWDTW'06) : Sochi, Russia, September 15-19, 20062006 / p. 282-286 : ill

book article

90

book article

A hybrid BIST architecture and its optimization for SoC testingJervan, Gert; Peng, Zebo; Ubar, Raimund-Johannes; Kruus, HelenaProceedings of the 3rd International Symposium on Quality Electronic Design : ISQED 2002, March 18-21, 2002, San Jose, California2002 / p. 273-279 : ill https://ieeexplore.ieee.org/document/996750

book article

91

journal article

Hybrid BIST methodology for testing core-based systemsJervan, Gert; Ubar, Raimund-Johannes; Peng, ZeboProceedings of the Estonian Academy of Sciences. Engineering2006 / 3-2, p. 300-322 : ill

journal article

92

book article

Hybrid BIST optimization for core-based systems with test pattern broadcastingUbar, Raimund-Johannes; Jenihhin, Maksim; Jervan, Gert; Peng, ZeboDELTA 2004 : second IEEE International Workshop on Electronic Design, Test and Applications : 28-30 January 2004, Perth, Australia : proceedings2004 / p. 3-8 : ill https://ieeexplore.ieee.org/document/1409808

book article

93

book article

Hybrid BIST optimization using reseeding and test set compactionJervan, Gert; Orasson, Elmet; Kruus, Helena; Ubar, Raimund-Johannes10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, DSD 2007 : 29-31 August 2007, Lübeck, Germany : proceedings2007 / p. 596-603 : ill http://dx.doi.org/10.1109/DSD.2007.4341529

book article

94

journal article

Hybrid BIST optimization using reseeding and test set compactionJervan, Gert; Orasson, Elmet; Kruus, Helena; Ubar, Raimund-JohannesMicroprocessors and microsystems2008 / 5/6, p. 254-262 : ill https://www.sciencedirect.com/science/article/abs/pii/S0141933108000288

journal article

95

book article

Hybrid BIST scheduling for NoC-based SoCsJervan, Gert; Shchenova, Tatjana; Ubar, Raimund-JohannesProceedings [of] 24th IEEE Norchip Conference : Linköping, Sweden, 20-21 November 20062006 / p. 141-144 : ill https://ieeexplore.ieee.org/document/4126966

book article

96

book article

Hybrid BIST time minimization for core-based systems with STUMPS architectureJervan, Gert; Eles, Petru; Peng, Zebo; Ubar, Raimund-Johannes; Jenihhin, Maksim18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems : 3-5 November 2003, Boston, Massachusetts : proceedings2003 / p. 225-232 : ill https://ieeexplore.ieee.org/document/1250116

book article

97

book

Hybrid built-in self-test and test generation techniques for digital systemsJervan, Gert2005 https://www.ester.ee/record=b2177537*est

book

98

journal article

IKT haridus ülikoolides läbi TTÜ arvutitehnika instituudi vaateprismaKruus, Margus; Jervan, GertArvutimaailm2010 / 5, lk. 8-9 : fot https://artiklid.elnet.ee/record=b2409375*est

journal article

99

book article

IMMizer : an innovative cost-effective method for minimizing assertion setsHeidari Iman, Mohammad Reza; Raik, Jaan; Jervan, Gert; Ghasempouri, Tara2022 25th Euromicro Conference on Digital System Design (DSD) : Maspalomas, Spain 2022 : proceedings2022 / p. 671 - 678 https://doi.org/10.1109/DSD57027.2022.00095 Article at Scopus Article at WOS

book article

Seotud publikatsioonid 1

Enhancing assertion-based verification in hardware designs through data mining algorithms = Andmekaeve algoritmide kasutamine riistvarasüsteemide väidete-põhise verifitseerimise parendamiseks

100

book article

An improved estimation methodology for hybrid BIST cost calculationJervan, Gert; Peng, Zebo; Ubar, Raimund-Johannes; Korelina, OlgaProceedings [of] 22nd NORCHIP Conference : Oslo, Norway, 8-9 November 20042004 / p. 297-300 : ill https://ieeexplore.ieee.org/document/1423882

book article

Jervan, Gert (TTÜ author)

types of item

author 19

name of the person 9

CV 7