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A synthesis-agnostic behavioral fault model for high gate-level fault coverage (title)
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book article
A synthesis-agnostic behavioral fault model for high gate-level fault coverage
Karputkin, Anton
;
Raik, Jaan
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) : proceedings
2016
/
p. 1124-1127 : ill
https://ieeexplore.ieee.org/document/7459477/figures#figures
book article
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keyword
22
1.
high-level fault coverage
2.
high-level control fault model
3.
high-level fault model
4.
high-level functional fault model
5.
high-level fault simulation
6.
fault coverage
7.
low-level fault redundancy
8.
fault analysis model
9.
functional fault model
10.
stuck-at fault model
11.
high level synthesis
12.
high-level decision diagrams (HLDD) synthesis
13.
high-level synthesis
14.
High-Level Synthesis (HLS)
15.
high-level synthesis for test
16.
local interpretable model-agnostic explanations (LIME)
17.
logic level and high level BDDs
18.
behavioral synthesis
19.
gate-level analysis
20.
gate-level circuit abstraction
21.
gate-level netlist
22.
register transfer and gate level simulation
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