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Exploiting high-level descriptions for circuits fault tolerance assessments (title)
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book article
Exploiting high-level descriptions for circuits fault tolerance assessments
Benso, A.
;
Prinetto, Paolo
;
Rebaudengo, M.
;
Sonza Reorda, Matteo
;
Raik, Jaan
;
Ubar, Raimund-Johannes
1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, October 20-22, 1997
1997
/
p. 212-216
https://ieeexplore.ieee.org/document/628327
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keyword
10
1.
high-level control fault model
2.
high-level fault coverage
3.
high-level fault model
4.
high-level fault simulation
5.
high-level functional fault model
6.
cross-layer fault tolerance
7.
fault tolerance
8.
fault-tolerance
9.
logic level and high level BDDs
10.
low-level fault redundancy
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