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126

journal article

Mixed-level test generator for digital systemsBrik, Marina; Jervan, Gert; Markus, Antti; Paomets, Priidu; Raik, Jaan; Ubar, Raimund-JohannesProceedings of the Estonian Academy of Sciences. Engineering1997 / 4, p. 271-282 : ill

journal article

127

dissertation

Model synthesis from VHDL for the functional test generation systemKrupnova, Helena1993 https://www.ester.ee/record=b2090509*est

dissertation

128

newspaper article

MS Estonia ferry investigation continues, no additional funds yet allocated [Online resources]Linnart, Martnews.err.ee2022 MS Estonia ferry investigation continues, no additional funds yet allocated

newspaper article

129

book article

Multi-level fault simulation of digital systems on decision diagramsUbar, Raimund-Johannes; Raik, Jaan; Ivask, Eero; Brik, MarinaThe First IEEE International Workshop on Electronic Design, Test and Applications : DELTA 2002, 29-31 January 2002, Christchurch, New Zealand : proceedings2002 / p. 86-91 : ill

book article

130

book

Multi-level test generation and fault diagnosis in digital systemsUbar, Raimund-Johannes1992

book

131

book article

Multi-level test generation for digital systems at system, circuit and defect levelsUbar, Raimund-JohannesProceedings of the 7th International Scientific Conference "Theory and Technique of Information Transmission, Reception and Processing" : Tuapse, October 1-4, 20012001 / p. 286-288

book article

132

book article

Multiple fault testing in systems-on-chip with high-level decision diagramsUbar, Raimund-Johannes; Oyeniran, Adeboye Stephen; Schölzel, Mario; Vierhaus, Heinrich TheodorProceedings of 2015 10th International Design & Test Symposium (IDT) : Dead Sea, Jordan, 14-16 December 20152015 / p. 66-71 : ill http://dx.doi.org/10.1109/IDT.2015.7396738

book article

133

book article

Multivalued simulation on AG-model of digital devicesUbar, Raimund-Johannes; Voolaine, AndrusProceedings of the 12th Conference on Fault-Tolerant Systems and Diagnostics, Prague, Czechoslovakia, September, 19891989 / p. 101-104

book article

134

book article

Mutation analysis for systemC designs at TLMGuarnieri, Valerio; Bombieri, Nicola; Pravadelli, Graziano; Fummi, Franco; Hantson, Hanno; Raik, Jaan; Jenihhin, Maksim; Ubar, Raimund-Johannes12th IEEE Latin American Test Workshop (LATW) : Porto de Galinhas, Brasil, 27-30 March 20112011 / [6] p https://ieeexplore.ieee.org/document/5985925

book article

135

dissertation

Mutation-based verification and error correction in high-level designs = Mutatsioonidel põhinev verifitseerimine ja vigade parandamine kõrgtaseme skeemidesHantson, Hanno2015 https://www.ester.ee/record=b4518212*est

dissertation

136

newspaper article

Mõtteid koostöö võimalikkusest Ida-Lääne piirilUbar, Raimund-Johannes; Kruus, MargusMente et Manu2003 / 20. okt., lk. 2 : portr https://artiklid.elnet.ee/record=b1415646*est

newspaper article

137

book article

New method of testability calculation to guide RT-level test generationRaik, Jaan; Nõmmeots, Tanel; Ubar, Raimund-Johannes4th IEEE Latin-American Test Workshop : LATW2003 : Natal, Brazil, February 16-19, 20032003 / p. 46-51 : ill https://link.springer.com/article/10.1007/s10836-005-5288-5

book article

138

book article

On correction of the results of a ternary simulation and a preliminary estimation of the correction resultsMatrosova, Anjela; Golubeva, O.; Oshlakova, T.BEC'98 : the 6th Biennial Conference on Electronics and Microsystems Technology, October 7-9, 1998, Tallinn, Estonia : proceedings1998 / p. 183-186: ill

book article

139

book article

On multiple fault detection in combinational logic circuitsBirger, AlexanderBEC'96 : the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings1996 / p. 225-228

book article

140

journal article EST / journal article ENG

Optimization of boundary scan tests using FPGA-based efficient scan architecturesAleksejev, Igor; Devadze, Sergei; Jutman, Artur; Shibin, KonstantinJournal of electronic testing : theory and applications (JETTA)2016 / p. 245-255 : ill https://doi.org/10.1007/s10836-016-5588-y Journal metrics at Scopus Article at Scopus Journal metrics at WOS Article at WOS

journal article EST / journal article ENG

141

book article

Optimization of memory-constrained hybrid BIST for testing core-based systemsJervan, Gert; Kruus, Helena; Orasson, Elmet; Ubar, Raimund-JohannesProceedings of the IEEE 2nd International Symposium on Industrial Embedded Systems : SIES'2007 : Lisbon, Portugal, 4-6 July 20072007 / p. 71-77 https://ieeexplore.ieee.org/document/4297319

book article

142

book article

Optimization of memory-constrained hybrid BIST for testing core-based systemsJervan, Gert; Kruus, Helena; Orasson, Elmet; Ubar, Raimund-JohannesInfo- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum2007 / lk. 133-136 : ill

book article

143

journal article

Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systemsUbar, Raimund-JohannesFacta Universitatis [Niš]. Series electronics and energetics2011 / p. 303-324 : ill http://dx.doi.org/10.2298/FUEE1103303U

journal article

144

book article

Overview about low-lewel and high-level decision diagrams for diagnostic modeling of digital systemsUbar, Raimund-JohannesProceedings of the Reed-Muller 2011 Workshop : May 25-26, 2011, Tuusula, Finland2011 / p. 1-10 : ill https://scindeks-clanci.ceon.rs/data/pdf/0353-3670/2011/0353-36701103303U.pdf

book article

145

book article

Overview of e-learning environment for web-based study of testing and diagnostics of digital systemsJutman, Artur; Ubar, Raimund-Johannes; Wuttke, Heinz-DietrichMicroelectronics education : proceedings of the 5th European Workshop on Microelectronics Education, held in Lausanne, Switzerland, April 15-16, 20042004 / p. 253-258 : ill https://link.springer.com/chapter/10.1007/978-1-4020-2651-5_41

book article

146

book article

Overview of e-learning environment for web-based study of testing and diagnostics of digital systemsJutman, Artur; Ubar, Raimund-Johannes; Wuttke, Heinz-Dietrich5th European Workshop on Microelectronics Education - EWME 2004, Lausanne, 20042004 / p. 173-176 https://link.springer.com/chapter/10.1007/978-1-4020-2651-5_41

book article

147

book article

Parallel critical path tracing fault simulationUbar, Raimund-Johannes39. Internationales Wissenschaftliches Kolloquium : 27.-30.09.1994. Bd. 1, Vortragsreihen1994 / S. 399-404

book article

148

journal article

Parallel fault simulation in digital circuitsAarna, Margit; Raik, Jaan; Ubar, Raimund-JohannesScientific proceedings of Riga Technical University. 7. serija, Telecommunications and electronics2001 / p. 91-94 : ill

journal article

149

book article

Parallel fault simulation in digital circuitsAarna, Margit; Raik, Jaan; Ubar, Raimund-JohannesProc. of 42nd International Scientific Conference of Riga Technical University2001 / p. 91-94

book article

150

book article

Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environmentHe, Zhiyuan; Jervan, Gert; Peng, Zebo; Eles, PetruProceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 20052005 / p. 83-86 : ill https://ieeexplore.ieee.org/document/1559782

book article

digitaaltehnika (subject term)

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