print

On test generation for microprocessors for extended class of functional faults

author
Oyeniran, Adeboye Stephen
Ubar, Raimund-Johannes
Jenihhin, Maksim
Raik, Jaan
statement of authorship
Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, and Jaan Raik
source
VLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers
location of publication
Cham
publisher
Springer Nature
year of publication
2020
pages
p. 21-44
conference name, date
27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, October 6–9, 2019
conference location
Cusco, Peru
url
https://doi.org/10.1007/978-3-030-53273-4
subject term
mikroprotsessorid
diagnostika (tehnika)
modelleerimine (teadus)
testimine
veaavastus
Scopus
Conference proceedings at Scopus
Article at Scopus
kvartiil
Q3
category (general)
Decision sciences
category (sub)
Decision sciences. Information systems and management
keyword
microprocessor testing
high-level functional fault model
test generation
high-level fault coverage
ISSN
1868-4238
ISBN
978-3-030-53272-7
notes
Bibliogr.: 41 ref
Open Access
Open Access
scientific publication
teaduspublikatsioon
classifier
3.1
TTÜ department
arvutisüsteemide instituut
language
inglise
Uurimisrühm
Centre for trustworthy and efficient computing hardware (TECH)
Centre of dependable computing systems
Oyeniran, A.S., Ubar, R., Jenihhin, M., Raik, J. On test generation for microprocessors for extended class of functional faults // VLSI-SoC: New technology enabler : 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 : Revised and Extended Selected Papers. Cham : Springer Nature, 2020. p. 21-44. https://doi.org/10.1007/978-3-030-53273-4