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51
book article
New method of testability calculation to guide RT-level test generation
Raik, Jaan
;
Nõmmeots, Tanel
;
Ubar, Raimund-Johannes
4th IEEE Latin-American Test Workshop : LATW2003 : Natal, Brazil, February 16-19, 2003
2003
/
p. 46-51 : ill
https://link.springer.com/article/10.1007/s10836-005-5288-5
book article
52
book article
On automatic software-based self-test program generation based on high-Level decision diagrams
Jasnetski, Artjom
;
Ubar, Raimund-Johannes
;
Tšertov, Anton
LATS 2016 : 17th IEEE Latin-American Test Symposium, Foz do Iguacu, Brazil, 6th-9th April 2016
2016
/
p. 177
http://dx.doi.org/10.1109/LATW.2016.7483357
book article
53
book article
On SSBDD model size & complexity
Jutman, Artur
ECS'03 : proceedings of the 4th Electronic Circuits and Systems Conference : September 11-12, 2003, Bratislava, Slovakia
2003
/
p. 17-22
https://pld.ttu.ee/~artur/papers/SSBDD_Model_Size-ECS03.pdf
book article
54
journal article
Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systems
Ubar, Raimund-Johannes
Facta Universitatis [Niš]. Series electronics and energetics
2011
/
p. 303-324 : ill
http://dx.doi.org/10.2298/FUEE1103303U
journal article
55
book article
Overview about low-lewel and high-level decision diagrams for diagnostic modeling of digital systems
Ubar, Raimund-Johannes
Proceedings of the Reed-Muller 2011 Workshop : May 25-26, 2011, Tuusula, Finland
2011
/
p. 1-10 : ill
https://scindeks-clanci.ceon.rs/data/pdf/0353-3670/2011/0353-36701103303U.pdf
book article
56
book article
Parallel fault analysis on structurally synthesized BDDs
Devadze, Sergei
;
Ubar, Raimund-Johannes
Info- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum
2007
/
lk. 47-50 : ill
book article
57
book article
Probabilistic equivalence checking based on high-level decision diagrams
Karputkin, Anton
;
Ubar, Raimund-Johannes
;
Tombak, Mati
;
Raik, Jaan
Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems : April 13-15, 2011, Gottbus, Germany
2011
/
p. 423-428 : ill
https://ieeexplore.ieee.org/document/5783130
book article
58
journal article
PSL assertion checking using temporally extended high-level decision diagrams
Jenihhin, Maksim
;
Raik, Jaan
;
Tšepurov, Anton
;
Ubar, Raimund-Johannes
Journal of electronic testing : theory and applications
2009
/
6, p. 289-300 : ill
https://pld.ttu.ee/home/maksim/phd_papers/%5B11%5D%20latw%2708.pdf
journal article
59
book article
PSL assertion checking with temporally extended high-level decision diagrams
Jenihhin, Maksim
;
Raik, Jaan
;
Tšepurov, Anton
;
Ubar, Raimund-Johannes
Proceedings of the 9th IEEE Latin-American Test Workshop : LATW2008 : February 17-20, 2008, Puebla, Mexico
2008
/
p. 49-54 : ill
https://pld.ttu.ee/~maksim/phd_papers/%5B11%5D%20latw%2708.pdf
book article
60
book article
PSL assertions based verification with HLDD tools
Jenihhin, Maksim
Info- ja kommunikatsioonitehnoloogia doktorikooli IKTDK teise aastakonverentsi artiklite kogumik : 11.-12. mai 2007, Viinistu kunstimuuseum
2007
/
lk. 17-20 : ill
book article
61
journal article EST
/
journal article ENG
Ranking strategic objectives in a strategy map based on logarithmic fuzzy preference programming and similarity method
Safari, Hossein
;
Khanmohammadi, Ehsan
;
Maleki, Meysam
;
Cruz-Machado, Virgilio
;
Ševtšenko, Eduard
Management Systems in Production Engineering
2019
/
p. 153-161 : ill
https://doi.org/10.1515/mspe-2019-0025
Journal metrics at Scopus
Article at Scopus
Journal metrics at WOS
Article at WOS
journal article EST
/
journal article ENG
62
book article
Register-transfer level deductive fault simulation using decision diagrams
Reinsalu, Uljana
;
Raik, Jaan
;
Ubar, Raimund-Johannes
BEC 2010 : 2010 12th Biennial Baltic Electronics Conference : proceedings of the 12th Biennial Baltic Electronics Conference : Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia
2010
/
p. 193-196 : ill
book article
63
book article
Remarks on different decision diagrams
Stankovic, Radomir S.
;
Ubar, Raimund-Johannes
;
Astola, Jaakko
Proceedings of the Reed-Muller 2011 Workshop : May 25-26, 2011, Tuusula, Finland
2011
/
p. 99-110 : ill
book article
64
book article
Simulation-based verification with APRICOT framework using high-level decision diagrams
Jenihhin, Maksim
;
Raik, Jaan
;
Tšepurov, Anton
;
Ubar, Raimund-Johannes
East-West Design & Test Symposium : Moscow, September 18-21, 2009
2009
/
p. 13-16 : ill
book article
65
book article
SoC and board modeling for processor-centric board testing
Tšertov, Anton
;
Ubar, Raimund-Johannes
;
Jutman, Artur
;
Devadze, Sergei
14th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : DSD 2011 : 31 August - 2 September 2011, Oulu, Finland : proceedings
2011
/
p. 575-582 : ill
https://ieeexplore.ieee.org/document/6037463
book article
66
book article
Software-based self-test generation for microprocessors with high-level decision diagrams
Ubar, Raimund-Johannes
;
Tšertov, Anton
;
Jasnetski, Artjom
;
Brik, Marina
LATW2014 : 15th IEEE Latin-American Test Workshop : Fortaleza, Brazil, March 12th-15th, 2014
2014
/
[6] p. : ill
book article
67
journal article
Software-based self-test generation for microprocessors with high-level decision diagrams
Jasnetski, Artjom
;
Ubar, Raimund-Johannes
;
Tšertov, Anton
;
Brik, Marina
Proceedings of the Estonian Academy of Sciences
2014
/
p. 48-61 : ill
https://artiklid.elnet.ee/record=b2665215*est
journal article
68
book
Software-based self-test with decision diagrams for microprocessors
Ubar, Raimund-Johannes
;
Jasnetski, Artjom
;
Tšertov, Anton
;
Oyeniran, Adeboye Stephen
2018
book
69
book article
Structural fault collapsing by superposition of BDDs for test generation in digital circuits
Ubar, Raimund-Johannes
;
Mironov, Dmitri
;
Raik, Jaan
;
Jutman, Artur
Proceedings of the Eleventh International Symposium on Quality Electronic Design ISQED 2010 : March 22-24, 2010 San Jose, California USA
2010
/
p. 250-257 : ill
https://ieeexplore.ieee.org/document/5450451
book article
70
book article
Structurally synthesized binary decision diagrams
Jutman, Artur
;
Peder, Ahti
;
Raik, Jaan
;
Tombak, Mati
;
Ubar, Raimund-Johannes
Boolean Problems : 6th International Workshop : September 23-24, 2004, Freiberg
2004
/
p. 271-278 : ill
book article
71
book article
Structurally synthesized multiple input BDDs for simulation of digital circuits
Ubar, Raimund-Johannes
;
Mironov, Dmitri
;
Raik, Jaan
;
Jutman, Artur
16th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2009 : Yasmine Hammamet, Tunesia, 13-19 December, 2009
2009
/
p. 451-454 : ill
http://dx.doi.org/10.1109/ICECS.2009.5410895
book article
72
journal article
Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation
Leveugle, R.
;
Ubar, Raimund-Johannes
Electron technology
1999
/
3, p. 282-287 : ill
journal article
73
book article
Synthesis of high-level decision diagrams for functional test pattern generation
Ubar, Raimund-Johannes
;
Raik, Jaan
;
Karputkin, Anton
;
Tombak, Mati
Proceedings of the 16th International Conference Mixed Design of Integrated Circuits and Systems MIXDES 2009 : Lodz, Poland, 25-27 June, 2009
2009
/
p. 519-524 : ill
book article
74
book article
Teaching diagnostic modeling of digital systems with decision diagrams [Electronic resource]
Ubar, Raimund-Johannes
;
Raik, Jaan
;
Mironov, Dmitri
;
Evartson, Teet
;
Orasson, Elmet
;
Aarna, Margit
;
Wuttke, Heinz-Dietrich
Proceedings of 12th IASTED International Conference on Computers and Advanced Technology in Education - CATE 2009 : St.Thomas, US, November 22-24, 2009
2009
/
p. 1-6. [CD-ROM]
book article
75
book article
Temporally extended high-level decision diagrams for PSL assertions simulation
Jenihhin, Maksim
;
Raik, Jaan
;
Tšepurov, Anton
;
Ubar, Raimund-Johannes
Proceedings : Thirteenth IEEE European Test Symposium : ETS 2008 : 25-29 May 2008, Verbania, Italy
2008
/
p. 61-68 : ill
https://ieeexplore.ieee.org/document/4556029
book article
Number of records 80, displaying
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