Oyeniran, A. S., Ubar, R., Jenihhin, M., Gürsoy, C. C., Raik, J.

full record print

Mixed-level identification of fault redundancy in microprocessors

author

Oyeniran, Adeboye Stephen

Ubar, Raimund-Johannes

Jenihhin, Maksim

Gürsoy, Cemil Cem

Raik, Jaan

statement of authorship

Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik

source

LATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 2019

location of publication

[S.l.]

publisher

IEEE

year of publication

2019

pages

6 p. : ill

conference name, date

20th IEEE Latin American Test Symposium, LATS 2019, March 11th - 13th 2019

conference location

Santiago,Chile

url

https://doi.org/10.1109/LATW.2019.8704591

ISSN

2373-0862

ISBN

978-1-7281-1756-0

978-1-7281-1757-7

notes

Bibliogr.: 31 ref

TTÜ department

arvutisüsteemide instituut

language

inglise

Märksõnad ja võtmesõnad

subject term

mikroprotsessorid

tõrketaluvus

diagnostika (tehnika)

keyword

processor core testing

high-level control fault model

high-level fault simulation

fault coverage

fault redundancy

Reserch Group

Centre for trustworthy and efficient computing hardware (TECH)

Centre of dependable computing systems

Oyeniran, A. S., Ubar, R., Jenihhin, M., Gürsoy, C. C., Raik, J. Mixed-level identification of fault redundancy in microprocessors // LATS 2019 : 20th IEEE Latin American Test Symposium : Santiago, Chile, March 11th - 13th 2019. [S.l.] : IEEE, 2019. 6 p. : ill. https://doi.org/10.1109/LATW.2019.8704591