prindi

Defect-oriented test- and layout-generation for standard-cell ASIC designs

autor
Sudbrock, Joachim
Raik, Jaan
Ubar, Raimund-Johannes
Kuzmicz, Wieslaw
Pleskacz, Witold A.
vastutusandmed
Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold Pleskacz
allikas
Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 2005
ilmumiskoht
Los Alamitos
kirjastus/väljaandja
IEEE Computer Society
ilmumisaasta
2005
leheküljed
p. 79-82 : ill
leitav
https://ieeexplore.ieee.org/document/1559781
märksõna
integraallülitused
digitaalintegraallülitused
testimine
ISBN
0-7695-2433-8
märkused
Bibliogr.: 11 ref
keel
inglise
Sudbrock, J., Raik, J., Ubar, R.-J., Kuzmicz, W., Pleskacz, W. Defect-oriented test- and layout-generation for standard-cell ASIC designs // Proceedings : DSD'2005 : 8th Euromicro Conference on Digital System Design : Architectures, Methods and Tools : Porto, Portugal, August 30 - September 3, 2005. Los Alamitos : IEEE Computer Society, 2005. p. 79-82 : ill. https://ieeexplore.ieee.org/document/1559781